Circuitry, apparatus and method for embedding a test status outcome within a circuit being tested

• US 6,209,110 B1
• Filed: 03/30/1998
• Issued: 03/27/2001
• Est. Priority Date: 03/30/1998
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Orso, William R., Chhor, Khushrav S.
• Primary Examiner(s): Chung, Phung M.
• Application Number:
  US09/050,242
• Time in Patent Office: 1,093 Days
• Field of Search: 714/718, 714/719, 714/720
• US Class Current: 714/718
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence

Abstract

An integrated circuit, a programming mechanism and a method are provided for programming test information upon non-volatile storage devices of the integrated circuit. The test information includes a pass/fail outcome arising from one or more test operations to which the integrated circuit is exposed. In addition to or in lieu of the test outcomes, test results of one or more parametric tests at select test operations can be measured from and programmed back into the integrated circuit. Test limits against which the test results can be compared may also be programmed into the integrated circuit. The test outcomes of various test operations, test results of various test parameters and test limits of the same or dissimilar test parameters are stored in separate non-volatile storage locations attributed to the integrated circuit. Those storage locations and, particularly, the bits contained therein are read either before the integrated circuit is packaged, after it is packaged, or after the packaged integrated circuit is shipped to customer. Programming test information as to that particular integrated circuit provides traceability of test operations performed, quality control of integrated circuits shipped, failure analysis of integrated circuits manufactured and, in some instances, lessened overall test time.

Claims

1. An integrated circuit, comprising:

a first non-volatile storage device formed in a first address location reserved for receiving information as to an outcome of a first electrical test performed upon the integrated circuit; and

a second non-volatile storage device formed in a second address location reserved for receiving information as to an outcome of a second electrical test performed upon the integrated circuit, wherein whether the second electrical test outcome information is received depends on the first electrical test outcome information stored in the first storage device.

2. The integrated circuit as recited in claim 1, wherein said first address location is in an address space exclusive of a third address location configured to store bits used to operate the integrated circuit.

3. The integrated circuit as recited in claim 1, wherein said first electrical test occurs prior to enclosing the integrated circuit within a package, and wherein the first electrical test outcome information is electrically readable after the integrated circuit is packaged.

4. The integrated circuit as recited in claim 1, wherein said first electrical test occurs after enclosing the integrated circuit within a package, and wherein the first electrical test outcome information is electrically readable after the integrated circuit is packaged.

5. The integrated circuit as recited in claim 1, wherein a first bit is programmed in the first address location if the outcome of the first electrical test indicates the integrated circuit passed the first electrical test, and a second bit is programmed in the second address location if the outcome of the second electrical test indicates the integrated circuit passed the second electrical test.

6. The integrated circuit as recited in claim 1, wherein the first address location is exclusive of the second address location.

7. The integrated circuit as recited in claim 1, further comprising disable logic coupled to said first and second non-volatile storage devices, wherein the disable logic is adapted to disable the integrated circuit from operating based on the contents of the first and second storage devices.

8. The integrated circuit as recited in claim 1, wherein the first and second address locations are adapted for receiving information from a programming mechanism external to the integrated circuit.

9. An apparatus for programming an integrated circuit, comprising:

a programming mechanism adapted to address a first storage location within the integrated circuit reserved for receiving first information as to the outcome of a first electrical test, and further adapted to address a second storage location within the integrated circuit reserved for receiving second information as to the outcome of a second electrical test, wherein whether the second storage location is addressed is dependent on the first information; and

a read mechanism adapted to read the first information during the second electrical test.

10. The apparatus as recited in claim 9, wherein the second electrical test includes parametric and functional test parameters the same as or different from parametric and functional test parameters used during the first electrical test.

11. The apparatus as recited in claim 9, wherein the first storage location is a non-volatile storage location.

12. The apparatus as recited in claim 9, wherein the first storage location is rendered a non-volatile storage location.

13. The apparatus as recited in claim 9, wherein the first bit is permanently stored within the first storage location.

14. The apparatus as recited in claim 9, wherein the programming mechanism is located external to the integrated circuit.

15. A method for testing operation of an integrated circuit, comprising:

programming first information into the integrated circuit identifying whether the integrated circuit passes a first testing operation;

reading the first information during a second testing operation subsequent to the first testing operation;

continuing the second testing operation based on the result of said reading the first information; and

if the second testing operation is continued, programming second information into the integrated circuit identifying whether the integrated circuit passes the second testing operation.

16. The method as recited in claim 15, wherein said programming first information comprises addressing a first storage location and writing a first bit into the first storage location, wherein the first storage location is exclusive of an address location used to store bits used to operate the integrated circuit.

17. The method as recited in claim 15, wherein said programming first information comprises sending a first bit of data through a conductor coupled to a first storage location absent previously addressing the first storage location.

18. The method as recited in claim 15, further comprising aborting the second testing operation if the first bit identifies the integrated circuit as not having passed the first testing operation.

19. The method as recited in claim 15, further comprising disabling operation of the integrated circuit if the first bit identifies the integrated circuit as not having passed the first testing operation.

20. The method as recited in claim 15, wherein said programming first information and programming second information comprise using a programming mechanism external to the integrated circuit.