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Method for analyzing probe yield sensitivities to IC design

  • US 6,210,983 B1
  • Filed: 06/15/1999
  • Issued: 04/03/2001
  • Est. Priority Date: 10/21/1998
  • Status: Expired due to Term
First Claim
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1. A method for predicting yield limits of semiconductor wafers in a factory, comprising the steps of:

  • generating a wafer probe test pareto;

    determininig a histogram of the distribution from a selected group from the wafer probe test pareto;

    extracting parametric data from a database from said histogram;

    screening the parametric data for values of the parametric data outside of a predetermined range;

    determining if an average value of said screened parametric data shows a sensitivity to variations in said parametric data;

    determining specification limits of said screened parametric data; and

    using said specification limits to form an operating window to show said sensitivity.

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