Polycrystalline silicon germanium films for forming micro-electromechanical systems

• US 6,210,988 B1
• Filed: 01/14/2000
• Issued: 04/03/2001
• Est. Priority Date: 01/15/1999
• Status: Expired due to Term

• Current Assignee: Regents of the University of California (University of California)
• Original Assignee: Regents of the University of California (University of California)
• Inventors: Howe, Roger T., King, Tsu-Jae, Franke, Andrea
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): COLEMAN, WILLIAM D
• Application Number:
  US09/483,222
• Time in Patent Office: 445 Days
• Field of Search: 438/48, 438/50, 438/52, 438/933, 257/19, 257/202, 333/186
• US Class Current: 438/50
• CPC Class Codes: B81B 2203/0118 Cantilevers
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2201/0109 Sacrificial layers not provided for in B81C2201/0107 - B81C2201/0108
• CPC Class Codes: B81C 2203/0735 Post-CMOS, i.e. forming the micromechanical structure after the CMOS circuit
• CPC Class Codes: Y10S 438/933 Germanium or silicon or Ge-Si on III-V

Abstract

This invention relates to micro-electromechanical systems using silicon-germanium films.

Claims

1. A process for forming a micro-electromechanical system, comprising:

depositing onto a substrate a sacrificial layer of silicon- germanium;

depositing onto the sacrificial layer a structural layer of silicon-germanium, where the germanium content of the sacrificial layer is greater than the germanium content of the structural layer; and

removing at least a portion of the sacrificial layer.

2. The process of claim 1, wherein the sacrificial layer is composed of Si_1-xGe_x, where 0.4≦

x≦

1.

3. The process of claim 1, wherein the sacrificial layer and the structural layer are deposited at a temperature of about 650°

C. or less.

4. The process of claim 1, wherein the sacrificial layer and the structural layer are deposited at a temperature of about 550°

C. or less.

5. The process of claim 1, wherein the sacrificial layer is completely removed.

6. The process of claim 1, further comprising forming one or more transistors on the substrate.

7. The process of claim 6, wherein the one or more transistors are formed before the sacrificial and structural layers are deposited onto the substrate.

8. The process of claim 6, wherein the one or more transistors are formed using Cu metallization.

9. The process of claim 6, wherein the one or more transistors are formed using Al metallization.

10. The process of claim 6, wherein the sacrificial and structural layers are deposited onto the substrate at a temperature of about 550°

C. or less.

11. The process of claim 6, wherein the one or more transistors are formed without metallization before the sacrificial and structural layers are deposited onto the substrate;

and further comprising metallizing the transistors after the sacrificial and structural layers are deposited onto the substrate.

12. The process of claim 6, wherein the one or more transistors are MOS transistors.

13. The process of claim 6, wherein the one or more transistors are bipolar transistors.

14. The process of claim 1 or claim 6, wherein the sacrificial layer is removed by exposure to a solution comprising hydrogen peroxide, ammonium hydroxide, and water.

15. The process of claim 1 or claim 6, wherein the sacrificial layer is removed by exposure to a solution comprising hydrogen peroxide.

16. The process of claim 1, wherein the germanium concentration of the structural layer varies through its depth.

17. The process of claim 16, further comprising removing portions of the structural layer to achieve a desired three-dimensional shape.

18. The process of claim 1, further comprising incorporating the system into an optical device.

19. A process for forming a micro-electromechanical system, comprising:

depositing onto a substrate a sacrificial layer of silicon oxide;

depositing onto the sacrificial layer a structural layer of Si_1-xGe_x, where 0<

x≦

1, at a temperature of about 650°

C. or less; and

removing at least a portion of the sacrificial layer.

20. The process of claim 19, wherein the sacrificial layer and the structural layer are deposited at a temperature of about 550°

C. or less.

21. The process of claim 19, wherein the sacrificial layer is completely removed.

22. The process of claim 19, further comprising forming one or more transistors on the substrate.

23. The process of claim 22, wherein the one or more transistors are formed before the sacrificial and structural layers are deposited onto the substrate.

24. The process of claim 22, wherein the one or more transistors are formed using Cu metallization.

25. The process of claim 22, wherein the one or more transistors are formed using Al metallization.

26. The process of claim 22, wherein the sacrificial and structural layers are deposited onto the substrate at a temperature of about 550°

C. or less.

27. The process of claim 22, wherein the one or more transistors are formed without metallization before the sacrificial and structural layers are deposited onto the substrate;

and further comprising metallizing the transistors after the sacrificial and structural layers are deposited onto the substrate.

28. The process of claim 22, wherein the one or more transistors are MOS transistors.

29. The process of claim 22, wherein the one or more transistors are bipolar transistors.

30. The process of claim 22, wherein the sacrificial layer is removed by exposure to a solution comprising HF.

31. The process of claim 19, wherein the sacrificial layer is removed by exposure to a solution comprising HF.

32. The process of claim 31, further comprising depositing amorphous silicon onto the substrate before the sacrificial layer is exposed to HF.

33. The process of claim 32, wherein two or more separate layers of amorphous silicon are deposited onto the substrate before the sacrificial layer is exposed to HF.

34. The process of claim 19, wherein the germanium concentration of the structural layer varies through its depth.

35. The process of claim 34, further comprising removing portions of the structural layer to achieve a desired three-dimensional shape.

36. The process of claim 19, further comprising incorporating the system into an optical device.

37. A process for forming a micro-electromechanical system, comprising:

depositing onto a substrate a sacrificial layer of polycrystalline germanium;

depositing onto the sacrificial layer a structural layer of Si_1-xGe_x, where 0<

x<

1 at a temperature of about 650°

C. or less; and

removing at least a portion of the sacrificial layer.

38. The process of claim 37, further including forming one or more transistors on the substrate.

39. The process of claim 38, wherein the one or more transistors are formed before the sacrificial and structural layers are deposited onto the substrate.

40. The process of claim 39, wherein the sacrificial and structural layers are deposited above the one or more transistors.

41. The process of claim 39, wherein the structural layer is deposited onto an upper level of a metal interconnect of the one or more transistors.

42. The process of claim 37 wherein the structural layer forms a ground plane.

43. A process for forming a micro-electromechanical system, comprising:

depositing onto a substrate a ground plane layer of Si_1-xGe_x, where 0.8>

x>

0.6;

depositing onto the ground plane layer a sacrificial layer;

depositing onto the sacrificial layer a structural layer of Si_1-xGe_x, where 0<

x≦

1 at a temperature of about 650°

C. or less; and

removing at least a portion of the sacrificial layer.