Method of fabricating an ETOX flash memory
First Claim
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1. A method of fabricating an ETOX flash memory adapted for a semiconductor substrate, the method comprising:
- providing the semiconductor substrate, the substrate comprising an active region isolated by an isolation structure therein;
forming a stacked word line perpendicularly across the isolation structure on the substrate;
forming a source region and a drain region in the active region isolated by the isolation structure on both sides of the stacked word line;
forming spacers on sidewalls of the stacked word line;
forming a first insulating layer over the substrate;
removing parts of the first insulating layer to form a patterned trench exposing the source region and the drain region, while the isolation structure at the same side of the source region is exposed, and the isolation region at the same side of the drain region is covered by the first insulating layer;
forming a first conductive material layer inside the trench to form a source line on the source region and the isolation structure at the same side of the source region and a landing pad on the drain region only;
forming a second insulating layer over the substrate;
removing parts of the second insulating layer to form a contact window that exposes the landing pad; and
forming a contact plug in the contact window and a bit line on the second insulating layer, wherein the contact plug is electrically connected to the drain region and the bit line.
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Abstract
A method of fabricating an ETOX flash memory. A low-resistance source line is formed on the substrate to string each source region in one source array by self-aligned process to substitute conventional buried source line. And at the same time, landing pads are formed on the each drain region by a self-aligned process to reduce the fabrication difficulty of the contact plug.
48 Citations
30 Claims
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1. A method of fabricating an ETOX flash memory adapted for a semiconductor substrate, the method comprising:
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providing the semiconductor substrate, the substrate comprising an active region isolated by an isolation structure therein;
forming a stacked word line perpendicularly across the isolation structure on the substrate;
forming a source region and a drain region in the active region isolated by the isolation structure on both sides of the stacked word line;
forming spacers on sidewalls of the stacked word line;
forming a first insulating layer over the substrate;
removing parts of the first insulating layer to form a patterned trench exposing the source region and the drain region, while the isolation structure at the same side of the source region is exposed, and the isolation region at the same side of the drain region is covered by the first insulating layer;
forming a first conductive material layer inside the trench to form a source line on the source region and the isolation structure at the same side of the source region and a landing pad on the drain region only;
forming a second insulating layer over the substrate;
removing parts of the second insulating layer to form a contact window that exposes the landing pad; and
forming a contact plug in the contact window and a bit line on the second insulating layer, wherein the contact plug is electrically connected to the drain region and the bit line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
forming a conductive material layer; and
performing a blanket etch back process until exposing the stacked word line.
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13. The method according to claim 1, wherein a material of the contact plug and bit line comprises tungsten.
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14. The method according to claim 1, wherein a material of the contact plug and bit line comprises aluminum.
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15. A method of fabricating an ETOX flash memory adapted for a semiconductor substrate, the method comprising:
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forming a plurality of parallel device isolation lines in the substrate;
forming a plurality of parallel stacked word lines on the substrate, wherein the stacked word lines are perpendicularly accross the device isolation lines;
forming a plurality of parallel source arrays and parallel drain arrays alternately positioned in the substrate between the neighboring stacked word lines, wherein each source array has a plurality of source regions separately positioned between device isolation lines and each drain array has a plurality of drain regions separately positioned between device isolation lines;
forming a plurality of spacers on sidewalls of the stacked word lines;
forming a first insulating layer to cover the device isolation lines surrounded by the stacked word lines and the drain regions only, while the source regions and the device isolation lines surrounded by the source regions and the stacked word lines are exposed;
forming a plurality of source lines on the source arrays and across the device lines surrounded by the source regions and the stacked word lines, and a plurality of landing pads on the drain regions only;
forming a second insulating layer over the substrate; and
forming a plurality of contact plugs in the second insulating layer and a plurality of parallel bit lines on the second insulating layers, wherein the contact plugs are electrically connected to the drain regions and the bit lines, and the bit lines are parallel to the device isolation lines. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30)
forming a conductive material layer over the substrate; and
performing a blanket etch back process until exposing the stacked word lines.
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29. The method according to claim 15, wherein a material of the contact plugs and bit lines comprises tungsten.
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30. The method according to claim 15, wherein a material of the contact plugs and bit lines comprises aluminum.
Specification
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Current AssigneeUnited Microelectronics Corporation
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Original AssigneeUnited Microelectronics Corporation
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InventorsLee, Robin, Chen, Hwi-Huang, Hong, Gary
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Primary Examiner(s)Smith, Matthew
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Assistant Examiner(s)YEVSIKOV, VICTOR V
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Application NumberUS09/498,330Time in Patent Office424 DaysField of Search438/296, 438/256, 438/257, 438/399, 438/210, 438/253, 438/254, 438/264US Class Current438/257CPC Class CodesH10B 41/30 characterised by the memory...H10B 69/00 Erasable-and-programmable R...
