Method for fabricating high density trench gate type power device

• US 6,211,018 B1
• Filed: 12/30/1999
• Issued: 04/03/2001
• Est. Priority Date: 08/14/1999
• Status: Expired due to Term

• Current Assignee: Uniloc 2017 LLC (FIG LLC (d/b/a Fortress Investment Group LLC))
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: Kim, Sang Gi, Nam, Kee Soo, Koo, Jin Gun, Roh, Tae Moon
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): ROCCHEGIANI, RENZO
• Application Number:
  US09/475,281
• Time in Patent Office: 460 Days
• Field of Search: 438/27, 438/135, 438/137, 438/138, 438/268
• US Class Current: 438/270
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode

Abstract

A semiconductor technique is disclosed. Particularly a low voltage high current power device for use in a lithium ion secondary battery protecting circuit, a DC-DC converter and a motor is disclosed. Further, a method for fabricating a high density trench gate type power device is disclosed. That is, in the present invention, a trench gate mask is used for forming the well and/or source, and for this purpose, a side wall spacer is introduced. In this manner, the well and/or source is defined by using the trench gate mask, and therefore, 1 or 2 masking processes are skipped unlike the conventional process in which the well mask and the source mask are separately used. The decrease in the use of the masking process decreases the mask align errors, and therefore, the realization of a high density is rendered possible. Consequently, the on-resistance which is an important factor for the power device can be lowered.

Claims

1. A method for fabricating a trench gate type power device, comprising the steps of:

a) forming an insulating layer upon a semiconductor substrate;

b) using a trench gate mask to pattern said insulating layer;

c) carrying out an ion implantation by using said insulating layer (thus patterned) as an ion implantation mask, for forming a well;

d) using said insulating layer as an ion implantation mask to carry out an ion implantation for forming a source;

e) forming a spacer insulating layer on side walls of said insulating layer;

f) using said insulating layer and said spacer insulating layer as etch masks to form a trench on said semiconductor substrate and to define a source region;

g) forming a gate insulating layer on inside walls of said trench;

h) filling a gate electrode material into said trench, with said gate insulating layer having been formed thereon; and

i) forming a source electrode electrically contacted to said source region, and forming a drain electrode electrically contacted to a rear face of said semiconductor substrate.

2. The method as claimed in claim 1, wherein said spacer insulating layer has a thickness of 2000-5000 Å

.

3. A method for fabricating a trench gate type power device, comprising the steps of:

a) forming a first insulating layer upon a semiconductor substrate;

b) using a well mask to pattern said first insulating layer, thereby obtaining a patterned first insulating layer;

c) implanting ions into the semiconductor substrate by using the patterned first insulating layer as an ion implantation mask;

d) forming a second insulating layer on top of the patterned first insulating layer and a portion of the semiconductor substrate which is not covered by the patterned first insulating layer;

e) using a trench gate mask to pattern said second insulating layer;

f) using said patterned first and second insulating layers as ion implantation masks to carry out an ion implantation for forming a source;

g) forming a spacer insulating layer on side walls of said first and second insulating layers;

h) using said first and second insulating layers and said spacer insulating layer as etch masks to form a trench on said semiconductor substrate and to define a source region;

i) forming a gate insulating layer on side walls of said trench;

j) filling a gate electrode material into said trench, with said gate insulating layer having been formed thereon;

k) selectively removing said second insulating layer;

l) etching an exposed portion of said semiconductor substrate after the step k), to form a source contact region; and

m) forming a source electrode electrically contacted to said source region, and forming a drain electrode electrically contacted to a rear face of said semiconductor substrate.

4. The method as claimed in claim 3, wherein said first insulating layer and said spacer insulating layer are silicon oxide layers, and said second insulating layer is a silicon nitride layer with a thickness of 3000-5000 Å

.

5. The method as claimed in claim 3, wherein said spacer insulating layer has a thickness of 2000-5000 Å

.

6. A method for fabricating a trench gate type power device, comprising the steps of:

a) forming an insulating layer upon a semiconductor substrate;

b) using a trench gate mask to pattern said insulating layer;

c) carrying out an ion implantation by using said insulating layer (thus patterned) as an ion implantation mask, for forming a well;

d) forming a spacer insulating layer on side walls of said insulating layer;

e) using said insulating layer and said spacer insulating layer as etch masks to form a trench on said semiconductor substrate;

f) forming a gate insulating layer on inside walls of said trench;

g) filling a gate electrode material into said trench, with said gate insulating layer having been formed thereon;

h) removing said spacer insulating layer;

i) using said insulating layer as an ion implantation mask to carry out an ion implantation for forming a source region; and

j) forming a source electrode electrically contacted to said source region, and forming a drain electrode electrically contacted to a rear face of said semiconductor substrate.

7. The method as claimed in claim 6, wherein said spacer insulating layers include the silicon oxide layer having a thickness of 1000-4000 Å

and a silicon nitride layer having a thickness of 1000-4000 Å

, respectively.

8. The method as claimed in claim 6, wherein at the second step, said insulating layer is patterned so as to make its side walls inclined.