Semiconductor chip package with fan-in leads

• US 6,211,572 B1
• Filed: 10/29/1996
• Issued: 04/03/2001
• Est. Priority Date: 10/31/1995
• Status: Expired due to Term

• Current Assignee: Tessera, Inc. (Adeia, Inc.)
• Original Assignee: Tessera, Inc. (Adeia, Inc.)
• Inventors: Karavakis, Konstantine, Fjelstad, Joseph
• Primary Examiner(s): Clark, Sheila V.
• Application Number:
  US08/739,303
• Time in Patent Office: 1,617 Days
• Field of Search: 257/759, 257/642, 257/760, 257/780, 257/781, 257/777, 257/787, 257/773, 257/784, 257/776
• US Class Current: 257/781
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/02313 Subtractive methods
• CPC Class Codes: H01L 2224/02331 Multilayer structure
• CPC Class Codes: H01L 2224/0235 Shape of the redistribution layers
• CPC Class Codes: H01L 2224/0236 Shape of the insulating layers therebetween
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/024 Material of the insulating layers therebetween
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/13008 Bump connector integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48 of an individual wire connector
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/4951 Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
• CPC Class Codes: H01L 23/498 Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers shape of the substrate H01L23/13
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A compliant semiconductor chip package with fan-in leads and a method for manufacturing the same. The package, or “assembly”, contains a multiplicity of bond ribbons connected between the contacts of a semiconductor chip and corresponding terminals on a top surface of a compliant layer. The compliant layer provides stress relief to the bond ribbons encountered during handling or affixing the assembly to an external substrate. The chip package also contains a dielectric layer adjacent to at least one end of the bond ribbons. The dielectric layer relieves mechanical stresses associated with the thermal mismatch of assembly and substrate materials during thermal cycling. The assembly can be manufactured without the need for any bond wiring tools since the bond ribbons are patterned and formed during a standard photolithographic stage within the manufacturing process. The manufacturing process is also amenable to simultaneous assembly of a multiplicity of undiced chips on a wafer or simultaneous assembly of diced chips in a processing boat.

Claims

1. A compliant semiconductor chip package assembly comprising:

a semiconductor chip having a plurality of peripheral chip contacts on a face surface thereof and a central region bounded by the peripheral chip contacts;

a first dielectric protective layer having a first surface, a second surface and apertures, wherein the first surface of the first dielectric layer is attached to the face surface of the semiconductor chip and the apertures are aligned so that the chip contacts are exposed;

a compliant layer having a top surface, a bottom surface and sloping peripheral edges, wherein the bottom surface of the compliant layer is joined to the second surface of the first dielectric layer within the central region of the semiconductor chip; and

a plurality of electrically conductive bond ribbons, each bond ribbon having a top surface, a bottom surface, a first end that electrically couples to a respective peripheral chip contact of the semiconductor chip, wherein each bond ribbon extends along the sloping edges to the top surface of the compliant layer and connects to a respective terminal.

2. The compliant semiconductor chip package of claim 1 further including a second dielectric protective layer having a first surface that is attached to the exposed package assembly elements, wherein the second dielectric layer has a plurality of apertures such that the bonding pads of the semiconductor chip are exposed.

3. The compliant semiconductor chip package of claim 1 further comprised of an encapsulant layer that is attached to the top surface of the bond ribbons.

4. The compliant semiconductor chip package of claim 3 wherein the encapsulant layer material is selected from the group consisting of a curable liquid, silicone, flexibilized epoxy, thermoplastic and gel.

5. The compliant semiconductor chip package of claim 1 wherein the plurality of package terminals are configured in an array having an area that is smaller than the area bound by the peripheral bonding pads on the face of the semiconductor chip.

7. The compliant semiconductor chip package of claim 1, wherein the compliant layer material is selected from the group consisting of silicone, flexibilized epoxy, a thermosetting polymer, fluoropolymer, thermoplastic polymer and polyimide.

8. The compliant semiconductor chip package of claim 1, wherein a plurality of bumped protrusions are provided and underly the plurality of package terminals such that an array of bumped package terminals is formed.

9. The compliant semiconductor chip package of claim 1, wherein the top surface of the compliant layer has a plurality of concavities underlying the plurality of package terminals such that an array of concave-like package terminals is formed.

6. A compliant semiconductor chip package assembly comprising:

a semiconductor chip having a plurality of peripheral chip contacts on a face surface thereof and a central region bounded by the peripheral chip contacts;

a first dielectric protective layer having a first surface, a second surface and apertures, wherein the first surface of the first dielectric layer is attached to the face surface of the semiconductor chip and the apertures are aligned so that the chip contacts are exposed;

a compliant layer having a top surface, a bottom surface and sloping peripheral edges, wherein the bottom surface of the compliant layer is joined to the second surface of the first dielectric layer within the central region of the semiconductor chip; and

a plurality of electrically conductive bond ribbons, each bond ribbon having a top surface a bottom surface, a first end that electrically couples to a respective peripheral chip contact of the semiconductor chip, wherein each bond ribbon extends along the sloping edges to the top surface of the compliant layer and connects to a respective terminal, wherein the peripheral edge of the compliant layer has a first transition region near the top surface of the compliant layer and a second transition region near the second surface of the first dielectric protective layer and wherein the first and second transition regions have a radius of curvature.

10. A compliant microelectronic assembly comprising:

a microelectronic element having a first surface and a plurality of contacts disposed on the first surface thereof;

a compliant layer over the first surface of said microelectronic element, said compliant layer having a bottom surface facing toward said first surface of said microelectronic element, a top surface facing upwardly away from said microelectronic element and one or more edge surfaces extending between said top and bottom surface;

conductive terminals overlying the top surface of said compliant layer; and

flexible bond ribbons over said compliant layer, said bond ribbons extending over said top surface and extending on one or more of said edge surfaces, said bond ribbons electrically connecting said contacts and said conductive terminals.

11. The assembly as claimed in claim 10, where in said contacts on said microelectronic elements are disposed in a first region of said first surface, said compliant layer overlies a second region of said first surface, and said one or more of said edge surfaces include one or more border edge surfaces extending along one or more borders between said first and second regions.

12. The assembly as claimed in claim 10, further comprising:

a first dielectric protective layer between the first surface of the microelectronic element have the compliant layer, the first dielectric layer having a plurality of apertures therein go that said contacts are accessible therethrough.

13. The assembly as claimed in claim 12, wherein said bond ribbons overlie said first dielectric protective layer and said compliant layer.

14. The assembly as claimed in claim 10, further comprising a dielectric cover layer over said compliant layer and said bond ribbons, wherein the dielectric cover layer has a plurality of apertures therein so that said terminals are accessible therethrough.

15. The assembly as claimed in claim 10, further comprising an encapsulant loyer over the exposed surface of the bond ribbons.

16. The assembly as claimed in claim 15, further comprising a second dielectric protective layer atop the encapsulant layer, wherein the second dielectric protective layer has a plurality of apertures therein so that said terminals are accessible therethrough.

17. The assembly as claimed in claim 10, further comprising a barrier metal atop one or more of the contacts.

18. The assembly as claimed in claim 10, wherein said microelectronic element, includes a plurality of undiced semiconductor chips on a wafer, said compliant layer including a plurality of regions, each said region overlying one said chip and having one or more of the conductive terminals connected to said chip.

19. The assembly as claimed in claim 10, wherein said microelectronic element includes a plurality of adjacent semiconductor chips arranged in an array to form a corresponding plurality of compliant semiconductor chip packages, said compliant layer including a plurality of regions, each said region overlying one said chip and having one or more of the conductive terminals connected to said chip.

20. The assembly as claimed in claim 10, wherein said edge surfaces of the compliant layer are sloping surfaces which extend in both vertical and horizontal directions.

21. A compliant microelectronic assembly comprising:

a microelectronic element having a first surface and a plurality of contacts disposed on the first surface thereof;

a compliant layer over the first surface of said microelectronic element, said compliant layer having a bottom surface facing toward said first surface of said microelectronic element, a top surface facing upwardly away from said microelectronic element and one or more edge surfaces extending between said top and bottom surface;

conductive terminals overlying the top surface of said compliant layer; and

flexible bond ribbons over said compliant layer, said bond ribbons extending over said top surface and extending on one or more of said edge surfaces, said bond ribbons electrically connecting said contacts and said conductive terminals,

said edge surfaces of the compliant layer being sloping surfaces which extend in both vertical and horizontal directions,

wherein at least some of said sloping edge surfaces have first transition regions near the top surface of the compliant layer and second transition regions near the bottom surface of the compliant layer, and wherein both the first and second transition regions have respective radii of curvature.