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Semiconductor chip package with fan-in leads

  • US 6,211,572 B1
  • Filed: 10/29/1996
  • Issued: 04/03/2001
  • Est. Priority Date: 10/31/1995
  • Status: Expired due to Term
First Claim
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1. A compliant semiconductor chip package assembly comprising:

  • a semiconductor chip having a plurality of peripheral chip contacts on a face surface thereof and a central region bounded by the peripheral chip contacts;

    a first dielectric protective layer having a first surface, a second surface and apertures, wherein the first surface of the first dielectric layer is attached to the face surface of the semiconductor chip and the apertures are aligned so that the chip contacts are exposed;

    a compliant layer having a top surface, a bottom surface and sloping peripheral edges, wherein the bottom surface of the compliant layer is joined to the second surface of the first dielectric layer within the central region of the semiconductor chip; and

    a plurality of electrically conductive bond ribbons, each bond ribbon having a top surface, a bottom surface, a first end that electrically couples to a respective peripheral chip contact of the semiconductor chip, wherein each bond ribbon extends along the sloping edges to the top surface of the compliant layer and connects to a respective terminal.

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