Method and circuit for driving power transistors in a half bridge configuration allowing for excessive negative swing of the output node and integrated circuit incorporating the circuit

• US 6,211,706 B1
• Filed: 06/10/1997
• Issued: 04/03/2001
• Est. Priority Date: 05/04/1995
• Status: Expired due to Term

• Current Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Choi, Chongwook Chris, Tam, David C.
• Primary Examiner(s): Wells, Kenneth B.
• Application Number:
  US08/872,450
• Time in Patent Office: 1,393 Days
• Field of Search: 327/309, 327/310, 327/530, 327/534, 327/587, 327/108, 327/382, 327/537, 327/546, 327/333, 327/545, 327/384, 327/385, 361/111, 363/17, 363/95, 363/98, 363/132, 326/80, 326/81
• US Class Current: 327/108
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor
• CPC Class Codes: H03K 2217/0081 Power supply means, e.g. to the switch driver

Abstract

A method and circuit for driving power transistors arranged in series in a half bridge configuration allowing for excessive negative swing of an output node between the transistors in the half bridge configuration. The series transistors are connected between a first voltage source and a common potential. A second voltage reference source is also provided. A terminal is connected to a common point coupled to anodes of intrinsic diodes of driver circuits for the power transistors. The second voltage source is connected between the common potential and the terminal so as to shift the level of the common point such that the intrinsic diodes will not forward bias due to negative output node transients generated by diode forward recovery and stray inductances. The circuit of the invention can also be incorporated in an integrated circuit including a single chip, e.g., a silicon chip.

Claims

1. A method of driving power transistors in a half bridge configuration and allowing for excessive negative swing of an output node located between the transistors in the half bridge configuration, said method comprising the steps of:

arranging first and second power transistors in series in a half bridge configuration between a first voltage and a common ground voltage with said output node being located between the first and second power transistors;

providing a pair of driver circuits, each for driving one of the power transistors, wherein at least a respective one of said driver circuits having at least one intrinsic diode;

providing a second voltage source between said common ground potential and an anode of said intrinsic diode to shift the level of said anode such that said intrinsic diode will not forward bias when negative transients are present at the output node; and

level shifting input signals supplied to said respective driver circuit from the level of said second voltage source to the level of said common ground potential.

2. The method recited in claim 1, wherein said second voltage source shifts the level of said anode to a negative potential with respect to the common ground potential.

3. The method recited in claim 1, further comprising the step of level shifting said input signals to the level of said second voltage source prior to level shifting said input signals from the level of said second voltage source to the level of said common ground potential.

4. The method recited in claim 1, further comprising the step of level shifting said input signals supplied to another of said driver circuits from the level of said second voltage source to the level of a third voltage.

5. A circuit for driving power transistors arranged in a half bridge configuration and allowing for excessive negative swing of an output node located between the transistors in the half bridge configuration, the power transistors being connected in series between a first voltage source and a common ground potential, the circuit comprising:

a pair of driver circuits, each for driving one of the power transistors, wherein at least a respective one of said driver circuits having at least one intrinsic diode;

a second voltage source provided between said common ground potential and an anode of said intrinsic diode to shift the level of said anode such that said intrinsic diode will not forward bias when negative transients are present at the output node; and

at least one level shift circuit connected to said second voltage source and to said respective driver circuit for level shifting, in combination with said respective driver circuit, input signals supplied to said level shift circuit from the level of said second voltage source to the level of said common ground potential.

6. The circuit recited in claim 5, wherein said second voltage source shifts the level of said anode to a negative potential with respect to the common ground potential.

7. The circuit recited in claim 5, further comprising another level shift circuit for level shifting said input signals to the level of said second voltage source prior to level shifting said input signals from the level of said second voltage source to the level of said common ground potential.

8. The circuit recited in claim 5, further comprising another level shift circuit for level shifting said input signals supplied to another of said driver circuits from the level of said second voltage source to the level of a third voltage.

9. A method of integrating, on a single integrated circuit chip, a circuit for driving power transistors in a half bridge configuration and allowing for excessive negative swing of an output node located between the transistors in the half bridge configuration, said method comprising the steps of:

arranging first and second power transistors in series in a half bridge configuration between a first voltage and a common ground potential with said output node being located between the first and second power transistors;

providing a pair of driver circuits, each for driving one of the power transistors, wherein at least a respective one of said driver circuits having at least one intrinsic diode;

providing a second voltage source between said common ground potential and an anode of said intrinsic diode to shift the level of said anode such that said intrinsic diode will not forward bias when negative transients are present at the output node; and

level shifting input signals supplied to said respective driver circuit from the level of said second voltage source to the level of said common ground potential.

10. The method recited in claim 9, wherein said second voltage source shifts the level of said anode to a negative potential with respect to the common ground potential.

11. The method recited in claim 9, further comprising the step of level shifting said input signals to the level of said second voltage source prior to level shifting said input signals from the level of said second voltage source to the level of said common ground potential.

12. The method recited in claim 9, further comprising the step of level shifting said input signals supplied to another of said driver circuits from the level of said second voltage source to the level of a third voltage.

13. A circuit integrated, on a single integrated circuit chip, for driving power transistors arranged in a half bridge configuration and allowing for excessive negative swing of an output node located between the transistors in the half bridge configuration, the power transistors being connected in series between a first voltage source and a common potential, the circuit comprising:

a pair of driver circuits, each for driving one of the power transistors, wherein at least a respective one of said driver circuits having at least one intrinsic diode;

a second voltage source provided between said common ground potential and an anode of said intrinsic diode to shift the level of said anode such that said intrinsic diode will not forward bias when negative transients are present at the output node; and

at least one level shift circuit connected to said second voltage source and to said respective driver circuit for level shifting, in combination with said respective driver circuits, input signals supplied to said level shift circuit from the level of said second voltage source to the level of said common ground potential.

14. The circuit recited in claim 13, wherein said second voltage source shifts the level of said anode to a negative potential with respect to the common ground potential.

15. The circuit recited in claim 13, further comprising another level shift circuit for level shifting said input signals to the level of said second voltage source prior to level shifting said input signals from the level of said second voltage source to the level of said common ground potential.

16. The circuit recited in claim 13, further comprising another level shift circuit for level shifting said input signals supplied to another of said driver circuits from the level of said second voltage source to the level of a third voltage.