Semiconductor integrated circuit incorporating therein clock supply circuit

• US 6,211,715 B1
• Filed: 03/30/1998
• Issued: 04/03/2001
• Est. Priority Date: 03/31/1997
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Corporation
• Inventors: Terauchi, Youji
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): Nguyen, Hai L.
• Application Number:
  US09/049,919
• Time in Patent Office: 1,100 Days
• Field of Search: 327/115, 327/117, 327/291, 327/293, 327/295, 327/296, 327/297, 327/299, 327/144, 327/145
• US Class Current: 327/295
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence

Abstract

A semiconductor integrated circuit incorporating therein a clock supply circuit drives a plurality of peripheral circuits using different frequency-divided clocks. In order to avoid enlargement of switching current there is provided a frequency-dividing circuit for dividing external clock supplied from a clock supply terminal, and a plurality of peripheral circuits which are operated by frequency-divided clocks. There is provided a first clock supply circuit which is capable of generating frequency-divided clock with the highest frequency among frequency-divided clocks required by the peripheral circuits, and a plurality of second clock supply circuits for generating frequency-divided clocks from frequency-divided clock of the first clock supply circuit. Wiring to connect the first clock supply circuit to second clock supply circuits becomes short, and the number of wiring is reduced. Therefore it becomes possible to reduce the switching current.

Claims

1. A semiconductor integrated circuit incorporating therein a plurality of peripheral circuits, each of which is operated by a respective plurality of frequency-divided clock signals that are derived from an external clock signal, comprising:

a first clock supply circuit block for generating at least one frequency-divided clock signal from said external clock signal; and

a plurality of second clock supply circuit blocks for generating the respective plurality of frequency-divided clock signals from said at least one frequency-divided clock signal of said first clock supply circuit block,

wherein all of the frequency-divided clock signals supplied to any one of the peripheral circuits is supplied by one of the second clock supply circuit blocks, and

wherein each of said plurality of said second clock supply circuit blocks receives only a single frequency different from each other and generates said respective frequency divided clock signals having only said single frequency and smaller frequencies.

2. A semiconductor integrated circuit as claimed in claim 1, wherein one of the second clock supply circuit blocks is provided for each of said peripheral circuits.

3. A semiconductor integrated circuit incorporating therein a clock supply circuit as claimed in claim 2, wherein a plurality of peripheral circuits are divided into blocks containing at least one of the second clock supply circuit blocks.

4. A semiconductor integrated circuit incorporating therein a clock supply circuit as claimed in claim 2, wherein said second clock supply circuit blocks are connected in a cascaded manner, the frequency-divided clock signal from said first clock supply circuit being supplied to a first of the second clock supply circuit blocks, one of the frequency-divided clock signals from said first of the second clock supply circuit blocks is supplied to a second of said second clock supply circuit blocks, and so forth such that a frequency-divided clock signal from an (n)-th of said second clock supply circuit blocks is supplied to an (n+1)-th of said second clock supply circuit blocks.

5. A semiconductor integrated circuit as claimed in claim 1, wherein each of the second clock supply circuit blocks supplies at least four frequency-divided clock signals to a corresponding one of the peripheral circuits.

6. A semiconductor integrated circuit as claimed in claim 5, wherein each of the second clock supply circuit blocks generates said at least four frequency-divided clock signals from a corresponding input frequency-divided clock signal, at least one of the four frequency-divided clock signals being equal to the corresponding input frequency-divided clock signal.

7. A semiconductor integrated circuit as claimed in claim 6, wherein said first clock supply circuit block generates four frequency-divided clock signals and supplies a different one to each second clock supply circuit block as the corresponding input frequency-divided clock signal for that second clock supply circuit block.

8. A semiconductor integrated circuit as claimed in claim 6, wherein, for N second supply circuit blocks, where N is a positive integer greater than 1, one of the frequency-divided signals generated by an n-th second supply circuit block is supplied as a corresponding input frequency-divided clock signal for an (n+1)-th second supply circuit block, where n is an integer equal between 1 and N−

1, inclusive.

9. A semiconductor integrated circuit as claimed in claim 6, wherein one of the second clock supply circuit blocks is provided for two of the peripheral circuits.

10. A method for supplying to a plurality of peripheral circuits a respective plurality of frequency-divided clock signals, each of a plurality of peripheral circuits incorporated on a semiconductor integrated circuit, said method comprising the steps of:

generating at least one frequency-divided clock signal from an external clock signal;

supplying said at least one frequency-divided clock signal to at least one of a plurality of clock supply circuit blocks;

generating the respective plurality of frequency-divided clock signals using the clock supply circuit blocks from said at least one frequency-divided clock; and

supplying to each of the peripheral circuits all of the frequency-divided clock signals used thereby from one of said clock supply circuit blocks;

feeding only a single frequency, different from each other, to each of said plurality of clock supply circuit blocks; and

generating, in said clock supply circuit blocks said respective plurality of frequency-divided clock signals having only said single frequency and smaller frequencies.

11. A method as claimed in claim 10, wherein each of the clock supply circuit blocks supply the frequency-divided clock signals to at least one of the peripheral circuits.

12. A method as claimed in claim 11, wherein said clock supply circuit blocks are connected in a cascaded manner, a first of the clock supply circuit blocks being supplied with said at least one frequency-divided clock signal, a second of said clock supply circuit blocks being supplied with an output from the first clock supply circuit block, and so forth such that an (n+1)-th of said clock supply circuit blocks is supplied with an output from an n-th of said clock supply circuit blocks.

13. A method as claimed in claim 10, further comprising the step of dividing a plurality of peripheral circuits into blocks containing at least one clock supply circuit block.

14. A semiconductor integrated circuit having a plurality of peripheral circuits, each operated by a respective plurality of frequency-divided clock signals, comprising:

a first clock supply circuit being supplied with an external clock signal and generating at least one frequency-divided signal from the external clock signal;

a plurality second clock supply circuits, each of which is provided for at least one of said peripheral circuits to provide said at least one peripheral circuit with all of the frequency-divided clock signals that are supplied to said at least one peripheral circuit; and

wherein each of said plurality of second clock supply circuits receives only a single frequency different from each other and generates said respective frequency-divided clock signals having only said single frequency and smaller frequencies.

15. A semiconductor integrated circuit as claimed in claim 14, wherein each of the second clock supply circuits supplies at least four frequency-divided clock signals to a corresponding one of the peripheral circuits.

16. A semiconductor integrated circuit as claimed in claim 15, wherein, for N second supply circuits, where N is a positive integer greater than 1, one of the frequency-divided signals generated by an n-th second supply circuit is supplied as a corresponding input frequency-divided clock signal for an (n+1)-th second supply circuit, where n is an integer equal between 1 and N−

1, inclusive.

17. A semiconductor integrated circuit as claimed in claim 15, wherein one of the second clock supply circuits is provided for two of the peripheral circuits.

18. A semiconductor integrated circuit as claimed in claim 15, wherein each of the second clock supply circuits generates said at least four frequency-divided clock signals from a corresponding input frequency-divided clock signal, at least one of the four frequency-divided clock signals being equal to the corresponding input frequency-divided clock signal.

19. A semiconductor integrated circuit as claimed in claim 15, wherein said first clock supply circuit generates four frequency-divided clock signals and supplies a different one to each second clock supply circuit as the corresponding input frequency-divided clock signal for that second clock supply circuit.

20. A semiconductor integrated circuit incorporating therein at least a first and a second peripheral circuit, said first peripheral circuit operated by a first plurality of frequency-divided clock signals and said second peripheral circuit operated by a second plurality of frequency-divided clock signals, said first and second plurality of frequency-divided clock signals derived from an external clock signal comprising:

an initial clock supply circuit block for generating an initial plurality of frequency-divided clock signals having at least a first initial frequency-divided clock signal f₁ and a second, different initial frequency-divided clock signal f₂,

at least first and second clock supply circuit blocks providing output to said first and second peripheral circuits respectively,

said first clock supply circuit block connected to said initial supply circuit block to receive only said first initial frequency-divided clock signal f₁ for generating said first plurality of frequency-divided clock signals having only frequencies of f₁ and smaller frequencies, and

said second clock supply circuit block connected to said initial supply circuit block to receive only said second initial frequency-divided clock signal f₂ for generating said second plurality of frequency-divided clock signals having only frequencies of f₂ and smaller frequencies.

21. A semiconductor integrated circuit comprising:

a first clock supply circuit for receiving a clock signal and for outputting a first clock signal and a second clock signal each having a different frequency-divide ratio;

a second clock supply circuit to which said first clock signal is inputted and in which said first clock signal is frequency-divided to form a frequency-divided first clock signal, the first clock signal and the frequency-divided first clock signal being supplied to a first peripheral circuit; and

a third clock supply circuit to which said second clock signal is inputted and in which said second clock signal is frequency-divided to form a frequency-divided second clock signal, the second clock signal and the frequency-divided second clock signal being supplied to a second peripheral circuit.

22. A semiconductor integrated circuit as claimed in claim 21, wherein the first clock supply circuit further outputs a third clock signal and a fourth clock signal, the first through fourth clock signals each having a different frequency-divide ratio and further comprising:

a fourth clock supply circuit to which said third clock signal is inputted and in which said third clock signal is frequency-divided to form a frequency-divided third clock signal, the third clock signal and the frequency-divided third clock signal being supplied to a third peripheral circuit; and

a fifth clock supply circuit to which said fourth clock signal is inputted and in which said fourth clock signal is frequency-divided to form a frequency-divided fourth clock signal, the fourth clock signal and the frequency-divided fourth clock signal being supplied to a fourth peripheral circuit.

23. A semiconductor integrated circuit as claimed in claim 21, wherein

said first peripheral circuit operates according to said first clock signal subjected to 1/n frequency division, and

said second peripheral circuit operates according to said second clock signal subjected to 1/n frequency division,

where ‘

n’

is an integer.

24. A semiconductor integrated circuit as claimed in claim 23, wherein

said first peripheral circuit operates according to said first clock signal subjected to 1, 1/2, . . . , 1/(2*N) frequency division, and

said second peripheral circuit operates according to said second clock signal subjected to 1, 1/2, . . . , 1/(2*N) frequency division,

where ‘

N’

is a positive integer.

25. A semiconductor integrated circuit comprising:

a first clock supply circuit for receiving a clock signal and for outputting a first clock signal;

a second clock supply circuit to which said first clock signal is inputted and in which said first clock signal is frequency-divided to form a frequency-divided first clock signal, the first clock signal and the frequency-divided first clock signal being supplied to a first peripheral circuit; and

a third clock supply circuit to which a second clock signal, which is the frequency-divided first clock signal, is inputted and in which said second clock signal is further frequency-divided to form a frequency-divided second clock signal, the second clock signal and the frequency-divided second clock signal being supplied to a second peripheral circuit.

26. A semiconductor integrated circuit as claimed in claim 25, wherein

said first peripheral circuit operates according to said first clock signal subjected to 1/n frequency division, and

said second peripheral circuit operates according to said second clock signal subjected to 1/n frequency division,

where ‘ n’

is an integer.

27. A semiconductor integrated circuit as claimed in claim 26, wherein

said first peripheral circuit operates according to said first clock signal subjected to 1, 1/2, . . . , 1/(2*N) frequency division, and

said second peripheral circuit operates according to said second clock signal subjected to 1, 1/2, . . . , 1/(2*N) frequency division,

where ‘

N’

is a positive integer greater than 1.

28. A semiconductor integrated circuit as claimed in claim 27, wherein

a fourth clock supply circuit to which a third clock signal, which is the frequency-divided second clock signal, is inputted and in which said third clock signal is further frequency-divided to form a frequency-divided third clock signal, the third clock signal and the frequency-divided third clock signal being supplied to a third peripheral circuit.

29. A semiconductor integrated comprising:

a first clock supply circuit for receiving a clock signal and for outputting a first clock signal;

a second clock supply circuit to which said first clock signal is inputted and in which said first clock signal is frequency-divided and supplied to first and second peripheral circuits as frequency-divided first clock signals; and

a third clock supply circuit to which a second clock signal, which is one of the frequency-divided first clock signals, is inputted and in which said second clock signal is further frequency-divided and supplied to third and fourth peripheral circuits.

30. A semiconductor integrated circuit as claimed in claim 29, wherein

said first and second peripheral circuits operate according to said first clock signal subjected to 1/n frequency division, and

said third and fourth peripheral circuits operate according to said second clock signal subjected to 1/n frequency division,

where ‘ n’

is an integer.

31. A semiconductor integrated circuit as claimed in claim 30, wherein

said first peripheral circuit operates according to said first clock signal subjected to 1, 1/2, . . . , 1/(2*N) frequency division, and

said second peripheral circuit operates according to said first clock signal subjected to 1/2, 1/4, . . . , 1/(2*N+1) frequency division,

where ‘

N’

is a positive integer greater than 1.

32. A semiconductor integrated circuit as claimed in claim 31, wherein

said third peripheral circuit operates according to said second clock signal subjected to 1, 1/2, . . . , 1/(2*N) frequency division, and

said fourth peripheral circuit operates according to said second clock signal subjected to 1/2, 1/4, . . . , 1/(2*N+1) frequency division.