Baseline wander compensation circuit and method

• US 6,211,716 B1
• Filed: 05/28/1999
• Issued: 04/03/2001
• Est. Priority Date: 05/28/1999
• Status: Expired due to Term

• Current Assignee: Micrel Incorporated (Microchip Technology Incorporated)
• Original Assignee: Kendin Communications, Inc. (Microchip Technology Incorporated)
• Inventors: Nguyen, Hai T., Chang, Menping
• Primary Examiner(s): TRAN, TOAN V
• Application Number:
  US09/322,247
• Time in Patent Office: 676 Days
• Field of Search: 327/307, 327/362, 327/363, 327/65, 327/67, 327/69, 327/72, 327/73
• US Class Current: 327/307
• CPC Class Codes: H03F 3/45973 by using a feedback circuit
• CPC Class Codes: H04L 25/064 Subtraction of the threshold from the signal, which is then compared to a supplementary fixed threshold

Abstract

An apparatus of compensating for offset in a received signal generated from a forward path stage, includes a first peak detector for receiving a first signal from the forward path stage and capable of detecting a peak of the first signal; a second peak detector for receiving a second signal from the forward path stage and capable of detecting a peak of the second signal; a differential amplifier coupled to the first peak detector and the second peak detector and capable of generating an offset control signal; and a compensation stage coupled to the differential amplifier and capable of compensating for offset in the received signal in response to the offset control signal. A method of compensating for offset in a received signal includes detecting a level of a first signal from a forward path stage; detecting a level of a second signal from the forward path stage; and generating an offset control signal to reduce an offset in the received signal in response to the level difference of the first signal and the second signal.

Claims

1. An apparatus for compensating for offset and Baseline Wander Effect in an input signal, comprising:

a forward path stage configured to receive a forward path input signal and to generate a first forward path output signal (P) and a second forward path output signal (M);

coupled to the forward path stage, a first peak detector configured to receive the first forward path output signal (P) from the forward path stage and capable of detecting a peak of the first forward path output signal (P), the first peak detector further capable of generating a peak signal (P_top) which is a value of the peak of the first forward path output signal (P);

coupled to the forward path stage, a second peak detector configured to receive the second forward path output signal (M) from the forward path stage and capable of detecting a peak of the second forward path output signal (M), the second peak detector further capable of generating a peak signal (M_top) which is a value of the peak of the second forward path signal (M);

a first window generator coupled to the first peak detector and configured to generate a top peak timing window in response to a pulse occurrence in the first forward path output signal (P);

a second window generator coupled to the second peak detector and configured to generate a bottom peak timing window in response to a pulse occurrence in the second forward path output signal (M);

wherein the top peak timing window enables the first peak detector to process the first forward path output signal (P) to generate the peak signal (P_top);

wherein the bottom peak timing window enables the second peak detector to process the second forward path output signal (M) to generate the peak signal (M_top);

a differential amplifier coupled to the first peak detector and the second peak detector and capable of generating an offset control signal based upon a difference between the peak signal (P_top) and the peak signal (M_top); and

a compensation stage coupled to the differential amplifier and capable of compensating for offset in the input signal in response to the offset control signal, the compensation stage further configured to generate the forward path input signal for input into the forward path stage.

2. The apparatus of claim 1 wherein at least one of the peak detectors comprises:

a comparator having a first input for receiving one of the first forward path output signal (P) and the second forward path output signal (M), a second input for receiving a peak level signal of one of the first forward path output signal (P), and the second forward path output signal (M), and an output;

a sample and block circuit coupled to the output of the comparator and capable of sampling a portion of one of the first forward path output signal (P) and the second forward path output signal (M), the portion of one of the first forward path output signal (P) and the second forward path output signal (M) being defined by the timing window received by the sample and block circuit;

a charge pump coupled to the sample and block circuit and capable of setting a value of the peak level signal based upon a control signal generated by the sample and block circuit; and

a timing window generator coupled to the sample and block circuit and capable of generating the timing window.

3. The peak detector of claim 2 wherein the sample and block circuit comprises:

a first transmission gate capable of receiving the timing window;

a second transmission gate coupled to the first transmission gate and capable of receiving the timing window;

a first transistor coupled to the first transmission gate and capable generating a first output control signal having a value dependent on values of the input signal and the timing window; and

a second transistor coupled to the second transmission gate and capable of generating a second output control signal having a value dependent on values of the input signal and the timing window.

4. The peak detector of claim 2 wherein the timing window generator comprises:

a delay stage for receiving one of the first forward path output signal (P) and the second forward path output signal (M);

an inverter coupled to the delay stage and capable of generating an inverted signal; and

an AND gate coupled to the inverter and capable of receiving one of the first forward path output signal (P) and the second forward path output signal (M), and the inverted signal to generate a timing window.

5. A method of compensating for offset in an input signal, the method comprising:

receiving the input signal by use of a forward path stage, the input signal comprising a first signal (P) and a second signal (M);

detecting a level of the first signal (P);

detecting a level of the second signal (M);

generating a top peak timing window in response to a pulse occurrence in the first signal (P), wherein the top peak timing window enables processing of the first signal (P) to generate a peak signal (P_top) representing a level of the first signal (P);

generating a bottom peak timing window in response to a pulse occurrence in the second signal (M), wherein the bottom peak timing window enables processing of the second forward path output signal (M) to generate a peak signal (M_top) representing a level of the second signal (M); and

generating an offset control signal to reduce an offset in the input signal in response to a difference between the peak signal (P_top) and the peak signal (M_top).

6. An apparatus for compensating for offset occurrence in an input signal, comprising:

a summing stage configured to receive the input signal comprising a first signal (P) and a second signal (M);

coupled to the summing stage, a forward path stage configured to transmit the first signal (P) and the second signal (M);

coupled to the forward path stage, a first peak detector configured to detect a peak level of the first signal (P);

coupled to the forward path stage, a second peak detector configured to detect a peak level of the second signal (M);

a first window generator coupled to the first peak detector and configured to generate a top peak timing window in response to a pulse occurrence in the first signal (P);

a second window generator coupled to the second peak detector and configured to generate a bottom peak timing window in response to a pulse occurrence in the second signal (M);

wherein the top peak timing window enables the first peak detector to process the first signal (P) to determine the peak level of the first signal (P);

wherein the bottom peak timing window enables the second peak detector to process the second signal (M) to determine the peak level of the second signal (M); and

a differential amplifier for comparing the peak levels of the first signal (P) and the second signal (M) and for generating a compensation control signal based on the comparison of the peak levels, the compensation control signal permitting the summing stage to perform compensation on the input signal.

7. An apparatus for compensating for offset occurrence in an input signal, comprising:

a summing stage configured to receive the input signal including a first signal (P) and a second signal (M);

coupled to the summing stage, a forward path stage configured to transmit the first signal (P) and the second signal (M);

coupled to the forward path stage, first means for detecting a level of the first signal (P) from the forward path stage;

coupled to the forward path stage, second means for detecting a level of the second signal (M) from the forward path stage;

a first window generator coupled to the first means and configured to generate a top peak timing window in response to a pulse occurrence in the first signal (P);

a second window generator coupled to the second means and configured to generate a bottom peak timing window in response to a pulse occurrence in the second signal (M);

wherein the top peak timing window enables the first means to process the first signal (P) to generate the peak signal (P_top);

wherein the bottom peak timing window enables the second means to process the second forward path output signal (M) to generate the peak signal (M_top); and

coupled the first means and second means, means for generating an offset control signal to reduce an offset in the input signal in response to the level difference of the first signal (P) and the second signal (M), the summing stage providing compensation to the input signal in response to the control signal.

8. An apparatus for compensating for offset and Baseline Wander Effect in an input signal, comprising:

a forward path stage configured to receive a forward path input signal and to generate a first forward path output signal (P) and a second forward path output signal (M);

coupled to the forward path stage, a first peak detector configured to receive the first forward path output signal (P) from the forward path stage and capable of detecting a peak of the first forward path output signal (P), the first peak detector further capable of generating a peak signal (P_top) which is a value of the peak of the first forward path output signal (P);

coupled to the forward path stage, a second peak detector configured to receive the second forward path output signal (M) from the forward path stage and capable of detecting a peak of the second forward path output signal (M), the second peak detector further capable of generating a peak signal (M_top) which is a value of the peak of the second forward path signal (M);

a differential amplifier coupled to the first peak detector and the second peak detector and capable of generating an offset control signal based upon a difference between the peak signal (P_top) and the peak signal (M_top);

a compensation stage coupled to the differential amplifier and capable of compensating for offset in the input signal in response to the offset control signal, the compensation stage further configured to generate the forward path input signal for input into the forward path stage;

wherein at least one of the peak detectors comprises;

a comparator having a first input for receiving one of the first forward path output signal (P) and the second forward path output signal (M), a second input for receiving a peak level signal of one of the first forward path output signal (P), and the second forward path output signal (M), and an output;

a sample and block circuit coupled to the output of the comparator and capable of sampling a portion of one of the first forward path output signal (P), and the second forward path output signal (M), the portion of one of the first forward path output signal (P), and the second forward path output signal (M) being defined by a timing window received by the sample and block circuit;

a charge pump coupled to the sample and block circuit and capable of setting a value of the peak level signal based upon a control signal generated by the sample and block circuit; and

a timing window generator coupled to the sample and block circuit and capable of generating the timing window;

wherein the sample and block circuit comprises;

a first transmission gate capable of receiving the timing window;

a second transmission gate coupled to the first transmission gate and capable of receiving the timing window;

a first transistor coupled to the first transmission gate and capable generating a first output control signal having a value dependent on values of the input signal and the timing window; and

a second transistor coupled to the second transmission gate and capable of generating a second output control signal having a value dependent on values of the input signal and the timing window.

9. An apparatus for compensating for offset and Baseline Wander Effect in an input signal, comprising:

a forward path stage configured to receive a forward path input signal and to generate a first forward path output signal (P) and a second forward path output signal (M);

coupled to the forward path stage, a first peak detector configured to receive the first forward path output signal (P) from the forward path stage and capable of detecting a peak of the first forward path output signal (P), the first peak detector further capable of generating a peak signal (P_top) which is a value of the peak of the first forward path output signal (P);

coupled to the forward path stage, a second peak detector configured to receive the second forward path output signal (M) from the forward path stage and capable of detecting a peak of the second forward path output signal (M), the second peak detector further capable of generating a peak signal (M_top) which is a value of the peak of the second forward path signal (M);

a differential amplifier coupled to the first peak detector and the second peak detector and capable of generating an offset control signal based upon a difference between the peak signal (P_top) and the peak signal (M_top);

a compensation stage coupled to the differential amplifier and capable of compensating for offset in the input signal in response to the offset control signal, the compensation stage further configured to generate the forward path input signal for input into the forward path stage;

wherein at least one of the peak detectors comprises;

a comparator having a first input for receiving one of the first forward path output signal (P) and the second forward path output signal (M), a second input for receiving a peak level signal of one of the first forward path output signal (P) and the second forward path output signal (M), and an output;

a sample and block circuit coupled to the output of the comparator and capable of sampling a portion of one of the first forward path output signal (P) and the second forward path output signal (M), the portion of one of the first forward path output signal (P) and the second forward path output signal (M) being defined by a timing window received by the sample and block circuit;

a charge pump coupled to the sample and block circuit and capable of setting a value of the peak level signal based upon a control signal generated by the sample and block circuit;

a timing window generator coupled to the sample and block circuit and capable of generating the timing window;

wherein the timing window generator comprises;

a delay stage for receiving one of the first forward path output signal (P) and the second forward path output signal (M);

an inverter coupled to the delay stage and capable of generating an inverted signal; and

an AND gate coupled to the inverter and capable of receiving one of the first forward path output signal (P) and the second forward path output signal (M), and the inverted signal to generate a timing window.

10. An apparatus for compensating for offset occurrence in an input signal, comprising:

a summing stage configured to receive the input signal comprising a first signal (P) and a second signal (M);

coupled to the summing stage, a forward path stage configured to transmit the first signal (P) and the second signal (M);

coupled to the forward path stage, a first peak detector configured to detect a peak level of the first signal (P);

coupled to the forward path stage, a second peak detector configured to detect a peak level of the second signal (M);

a first window generator coupled to the first peak detector and configured to generate a top peak timing window in response to a pulse occurrence in the first signal (P);

a second window generator coupled to the second peak detector and configured to generate a bottom peak timing window in response to a pulse occurrence in the second signal (M);

wherein the top peak timing window enables the first peak detector to process the first signal (P) to determine the peak level of the first signal (P), the top peak timing window permitting the selective sampling of pulses of the first signal (P) to determine the peak level of the first signal (P);

wherein the bottom peak timing window enables the second peak detector to process the second signal (M) to determine the peak level of the second signal (M), the bottom peak timing window permitting the selective sampling of pulses of the second signal (M) to determine the peak level of the second signal (M); and

a differential amplifier for comparing the peak levels of the first signal (P) and the second signal (M) and for generating a compensation control signal based on the comparison of the peak levels, the compensation control signal permitting the summing stage to perform compensation on the input signal.