Clock and data recovery PLL based on parallel architecture

• US 6,211,741 B1
• Filed: 04/29/1999
• Issued: 04/03/2001
• Est. Priority Date: 10/16/1998
• Status: Active Grant

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Dalmia, Kamal
• Primary Examiner(s): KINKEAD, ARNOLD M
• Application Number:
  US09/302,214
• Time in Patent Office: 705 Days
• Field of Search: 375/374, 375/376, 331/1 A, 331/25, 331/11, 331/12, 327/147, 327/156, 327/158, 327/159, 455/260
• US Class Current: 331/11
• CPC Class Codes: H03D 13/004 the logic means delivering pulses at more than one terminal, e.g. up and down pulses
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/14 for assuring constant frequency when supply or correction voltages fail or are interrupted
• CPC Class Codes: H03L 7/191 using at least two different signals from the frequency divider or the counter for determining the time difference H03L7/193, H03L7/195 take precedence
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

An apparatus comprising a first circuit and a clock circuit. The first circuit may be configured to generate an output signal and a re-timed data signal in response to (i) a data input signal, (ii) a first clock signal and (iii) a second clock signal. The clock circuit may be configured to generate the first and second clock signals in response to the output signal.

Claims

1. An apparatus comprising:

a first circuit configured to generate an output signal and a re-timed data signal in response to (i) a data input signal, (ii) a first clock signal and (iii) a second clock signal; and

a clock circuit configured to generate said first and second clock signals in response to said output signal, wherein said clock circuit comprises (i) an N-rate VCO configured to generate N-subclocks and (ii) N/2 gates configured to generate said first and second clocks in response to said N-subclocks.

2. The apparatus according to claim 1, wherein said first circuit comprises N/2 phase detectors.

3. The apparatus according to claim 2, wherein said N/2 phase detectors operate at an N/2 bit rate.

4. The apparatus according to claim 2, wherein at least one of said phase detectors operates on a first edge of said data input signal and another one of said phase detectors operates on a second edge of said data input signal.

5. The apparatus according to claim 3, wherein said first circuit further comprises an N/2 rate charge pump.

6. The apparatus according to claim 1, wherein:

said N-rate VCO comprises a quarter rate VCO; and

said N/2 gates comprise two or more gates.

7. The apparatus according to claim 6, wherein said first circuit further comprises:

a first half-rate phase detector and a second half-rate phase detector.

8. The apparatus according to claim 7, wherein said first phase detector operates on a first edge of said data input signal and said second phase detector operates on a second edge of said data input signal.

9. The apparatus according to claim 5, wherein said first circuit further comprises a half-rate charge pump.

10. An apparatus comprising:

means for generating an output signal and a re-timed data signal in response to (i) a data input signal, (ii) a first clock signal and (iii) a second clock signal; and

means for generating said first and second clock signals in response to said output signal, wherein means for generating said first and second clock signals comprises (i) an N-rate VCO configured to generate N-subclocks and (ii) N/2 gates configured to generate said first and second clocks in response to said N-subclocks.

11. A method for clock and data recovery comprising the steps of:

(A) generating an output signal and a re-timed data signal in response to (i) a data input signal, (ii) a first clock signal and (iii) a second clock signal;

(B) generating N-subclocks; and

(C) generating said first and second clock signals in response to said output signal and said N-subclocks.

12. The method according to claim 11, wherein said first and second clock signals are generated with a voltage controlled oscillator.

13. The method according to claim 11, wherein step (A) generates said output signal and said re-timed data signal using N/2 phase detectors.

14. The method according to claim 13, wherein said N/2 phase detectors operate at an N/2 bit rate.