Liquid crystal display and method for manufacturing the same

• US 6,211,928 B1
• Filed: 06/10/1997
• Issued: 04/03/2001
• Est. Priority Date: 03/26/1996
• Status: Expired due to Term

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Electronics, Inc. (LG Corporation)
• Inventors: Ha, Yong-Min, Oh, Young-Jin, Lim, Kyoung-Nam, Kim, Jeong-Hyun
• Primary Examiner(s): Sikes, William L.
• Assistant Examiner(s): Duong, Tai V.
• Application Number:
  US08/872,368
• Time in Patent Office: 1,393 Days
• Field of Search: 349/43, 349/44, 349/122, 349/38, 349/110, 349/111, 257/59, 257/72, 345/92, 438/30
• US Class Current: 349/43
• CPC Class Codes: G02F 1/133357 Planarisation layers
• CPC Class Codes: G02F 1/133512 Light shielding layers, e.g. black matrix G02F1/136209 takes precedence
• CPC Class Codes: G02F 1/136209 Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2202/104 poly-Si
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 21/28158 Making the insulator
• CPC Class Codes: H01L 23/293 Organic, e.g. plastic
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78636 with supplementary region or layer for improving the flatness of the device
• CPC Class Codes: H01L 29/78669 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A liquid crystal display includes a substrate; a transistor over the substrate, the transistor having a gate, a source, and a drain; a passivation layer over the transistor; a light shielding layer over a portion of the passivation layer over the transistor; a planarization layer over the light shielding layer and the passivation layer, the planarization layer having a contact hole over one of the source and the drain; a pixel electrode over the planarization layer, the pixel electrode being connected to the one of the source and the drain through the contact hole; and an alignment layer over the pixel electrode.

Claims

1. A liquid crystal display comprising:

a substrate;

a transistor over the substrate, the transistor having a gate, a source, and a drain;

a passivation layer over the transistor;

a light shielding layer on a portion of the passivation layer over the transistor, the light shielding layer made of a black resin having thickness above 1 μ

m;

a planarization layer over the light shielding layer and the passivation layer, the planarization layer having a contact hole over one of the source and the drain;

a pixel electrode over the planarization layer, the pixel electrode being connected to the one of the source and the drain through the contact hole; and

an alignment layer over the pixel electrode.

2. The liquid crystal display according to claim 1, further comprising a gate bus line and a data bus line over the substrate, the gate bus line being connected to the gate of the transistor and the data bus line being connected to one of the source and the drain, wherein the light shielding layer covers the gate bus line and the data bus line.

3. The liquid crystal display according to claim 2, wherein a portion of the pixel electrode overlaps at least one of the data bus line and the gate bus line.

4. The liquid crystal display according to claim 1, wherein the planarization layer is an organic insulation material.

5. The liquid crystal display according to claim 4, wherein the organic insulation material includes benzocyclobutene.

6. The liquid crystal display according to claim 1, wherein the planarization layer includes a material of spin on glass.

7. The liquid crystal display according to claim 1, wherein the passivation layer includes an inorganic insulation layer.

8. The liquid crystal display according to claim 7, wherein the inorganic insulation layer includes one of SiN_x and SiO₂.

9. The liquid crystal display according to claim 7, wherein the planarization layer includes a material of spin on glass.

10. The liquid crystal display according to claim 7, wherein the planarization layer includes an organic insulation material.

11. The liquid crystal display according to claim 10, wherein the organic insulation material includes benzocyclobutene.

12. A method for manufacturing a liquid crystal display having a substrate, comprising:

forming a transistor over the substrate, the transistor having a gate, a drain, and a source;

forming a light shielding layer made of a black resin having a thickness above 1 μ

m over the transistor;

forming a planarization layer over an overall surface of the substrate including the light shielding layer; and

forming an alignment layer over the planarization layer.

13. The method according to claim 12, further comprising the step of forming a passivation layer over the transistor before the light shielding layer forming step.

14. The method according to claim 13, wherein the passivation layer includes one of SiN_x and SiO₂.

15. The method according to claim 12, wherein the planarization layer includes an organic insulation material.

16. The method according to claim 15, wherein the organic insulation material includes benzocyclobutene.

17. The method according to claim 12, wherein the planarization layer includes a material of spin on glass.

18. The method according to claim 12, further comprising the steps of:

forming a gate bus line over the substrate, the gate bus line being connected to the gate of the transistor; and

forming a data bus line over the substrate, the data bus line being connected to one of the source and the drain,

wherein the light shielding layer is formed to cover the gate bus line and the data bus line.

19. The method according to claim 18, further comprising the step of forming a pixel electrode over the substrate before the alignment layer forming step, the pixel electrode being connected to one of the source and drain.

20. The method according to claim 19, wherein a portion of the pixel electrode is formed to overlap at least one of the data bus line and the gate bus line.

21. A liquid crystal display comprising:

a substrate;

a transistor over the substrate, the transistor having a gate, a source, and a drain;

a pixel electrode contacting one of the source and drain;

a passivation layer over the transistor and the pixel electrode;

a light shielding layer on a portion of the passivation layer over the transistor, the light shielding layer made of a black resin having thickness above 1 μ

m;

a planarization layer over the light shielding layer and the passivation layer; and

an alignment layer over the planarization layer.

22. The liquid crystal display according to claim 21, further comprising a gate bus line and a data bus line over the substrate, the gate bus line being connected to the gate of the transistor and the data bus line being connected to one of the source and the drain, wherein the light shielding layer covers the gate bus line and the data bus line.

23. The liquid crystal display according to claim 22, wherein a portion of the pixel electrode overlaps at least one of the data bus line and the gate bus line.

24. The liquid crystal display according to claim 21, wherein the planarization layer is an organic insulation material.

25. The liquid crystal display according to claim 24, wherein the organic insulation material includes benzocyclobutene.

26. The liquid crystal display according to claim 21, wherein the planarization layer includes a material of spin on glass.

27. The liquid crystal display according to claim 21, wherein the passivation layer includes an inorganic insulation layer.

28. The liquid crystal display according to claim 27, wherein the inorganic insulation layer includes one of SiN_x and SiO₂.

29. The liquid crystal display according to claim 27, wherein the planarization layer includes a material of spin on glass.

30. The liquid crystal display according to claim 27, wherein the planarization layer includes an organic insulation material.

31. The liquid crystal display according to claim 30, wherein the organic insulation material includes benzocyclobutene.