Dynamic memory array having write data applied to selected bit line sense amplifiers before sensing to write associated selected memory cells

• US 6,212,109 B1
• Filed: 08/11/1999
• Issued: 04/03/2001
• Est. Priority Date: 02/13/1999
• Status: Expired due to Term

• Current Assignee: InnoMemory, LLC (Jeffrey M. Gross), Robert J. Proebsting
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Proebsting, Robert J.
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US09/372,320
• Time in Patent Office: 601 Days
• Field of Search: 365/190, 365/230.03, 365/189.01, 365/233
• US Class Current: 365/189.16
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/104 Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
• CPC Class Codes: G11C 2207/229 Timing of a write operation
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: H10B 12/488 Word lines
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures

Abstract

A high performance dynamic memory array architecture is disclosed in several embodiments, along with various embodiments of associated supporting circuitry. In an exemplary embodiment during an internal write operation, write circuitry supplies a small differential voltage to the selected bit line sense amplifiers, which “swallows” the normal read signal, before bit line sensing. The bit line sense amplifiers then “write” the level into the memory cell during normal latching. This provides for internal write operations which proceed, for many embodiments, at the same speed as internal read operations by letting a selected bit line sense amplifier restore the voltage levels onto the selected bit lines in accordance with the data to be written, rather than in accordance with the data previously stored in a selected memory cell. A write cycle may be designed to take the same very short time as a read cycle, rather than the longer time typically required to first sense old data, then modify it with the data to be written. The address and data for a write cycle are preferably queued to eliminate dead cycles on the data bus, and the actual write operation to physically store the write data into the selected memory cells postponed at least until the next external write cycle is received.

Claims

1. An integrated circuit including a dynamic memory array having individual memory cells organized as rows and columns, each row corresponding to one of a plurality of word lines and each column corresponding to one of a plurality of true and complement bit line pairs, a memory cell at a given row and column being coupled to the corresponding word line and coupled to either the true or complement corresponding bit line, said integrated circuit comprising:

a first array block including a first plurality of true and complement bit line pairs;

a first plurality of bit line sense amplifiers, each coupled to a respective one of the first plurality of bit line pairs, and each responsive to a sense amplifier enable signal;

a first complementary pair of local bus lines associated with the first plurality of bit line sense amplifiers;

a first plurality of coupling circuits, each associated with a respective one of the first plurality of bit line sense amplifiers, each arranged to receive a differential write data signal on the first complementary pair of local bus lines and, when selected for writing, to communicate a corresponding differential write signal to the respective one of the first plurality of bit line sense amplifiers prior to latching the first plurality of bit line sense amplifiers;

a first complementary pair of global input bus lines associated with the first plurality of bit line pairs and further associated with a respective plurality of bit line pairs located within respective array blocks other than the first array block;

a second coupling circuit arranged to receive a differential write data signal on the first complementary pair of global input bus lines and to communicate the differential write data signal to the first complementary pair of local bus lines; and

a sense amplifier enable control circuit for generating the sense amplifier enable signal for the first plurality of bit line sense amplifiers at a time during a memory cycle substantially irrespective of whether the memory cycle is a read cycle or a write cycle.

2. An integrated circuit as in claim 1 further comprising:

a first complementary pair of global output bus lines associated with the first plurality of bit line pairs and further associated with a respective plurality of bit line pairs located within respective array blocks other than the first array block.

3. An integrated circuit as in claim 1 wherein the second coupling circuit comprises:

a direct wired connection of the first complementary pair of local bus lines respectively to the first complementary pair of global input bus lines, thereby respectively connecting the true and complement bus lines of the first complementary pair of local bus lines directly to the true and complement bus lines of the first complementary pair of global input bus lines.

4. An integrated circuit as in claim 3 wherein each respective one of the first coupling circuits comprises:

a respective pair of coupling transistors connecting the first complementary pair of local bus lines to the respective bit line sense amplifier; and

a respective gating circuit for coupling, during a write cycle if the corresponding memory cell is to be written, a respective column select signal to gate terminals of the respective pair of coupling transistors.

5. An integrated circuit as in claim 4 wherein each respective gating circuit comprises:

a first transistor having a source terminal coupled to receive the respective column select signal, a drain terminal coupled to gate terminals of the respective pair of coupling transistors, and a gate terminal; and

a second transistor having a source terminal coupled to receive a first write control signal, a gate terminal coupled to receive a second write control signal, and a drain terminal coupled to the gate terminal of the first transistor;

whereby a respective gating circuit turns on its respective pair of coupling transistors when both the first and second write control signals are enabled and the respective column select signal is then driven active.

6. An integrated circuit as in claim 5 wherein:

the first write control signal comprises a signal which is enabled during a write cycle when one of the first plurality of bit line pairs is addressed during a write cycle; and

the second write control signal comprises a signal which is enabled during a write cycle when the write data signal corresponds to a data bit which is enabled for writing.

7. An integrated circuit as in claim 6 wherein:

the second write control signal comprises a byte write signal which is enabled during a write cycle when the write data signal corresponds to a data bit within a byte of an external data word, which byte is enabled for writing.

8. An integrated circuit as in claim 6 wherein:

the second write control signal remains active through consecutive memory cycles when the corresponding data bit is enabled for writing during each of the consecutive memory cycles.

9. An integrated circuit as in claim 1 wherein the second coupling circuit comprises:

a pair of transistors respectively connecting, when enabled by a write control signal, the first complementary pair of local bus lines to the first complementary pair of global input bus lines.

10. An integrated circuit as in claim 9 wherein each respective one of the first coupling circuits comprises:

a respective pair of coupling transistors connecting the first complementary pair of local bus lines to the respective bit line sense amplifier; and

a respective gating circuit for coupling, during a write cycle, a respective column select signal for the respective bit line sense amplifier to gate terminals of the respective pair of coupling transistors.

11. An integrated circuit as in claim 1 wherein each of the first plurality of bit line sense amplifiers includes:

a true internal sense amplifier node and a complement internal sense amplifier node, together forming a complementary pair of internal sense amplifier nodes; and

a first pair of array select transistors respectively coupling the true and complement internal sense amplifier nodes to the true and complement bit lines of the respective one of the first plurality of bit line pairs;

wherein each of the first pair of array select transistors for each of the first plurality of bit line sense amplifiers is gated by a first array select signal.

12. An integrated circuit as in claim 11 further comprising:

an array select control circuit for generating the first array select signal, for a given address during a memory cycle, having a waveshape substantially independent of whether the memory cycle is a read cycle or a write cycle.

13. An integrated circuit as in claim 12 wherein each of the first plurality of bit line sense amplifiers includes:

a second pair of array select transistors respectively coupling its true and complement internal sense amplifier nodes to true and complement bit lines of a corresponding second pair of bit lines located within an array block adjacent to the first array block;

wherein each of the second pair of array select transistors for each of the first plurality of bit line sense amplifiers is gated by a second array select signal.

14. An integrated circuit as in claim 1 further comprising:

a write data driver circuit coupled to the first complementary pair of global input bus lines for generating a differential write data signal thereupon which is of a magnitude substantially less than a power supply voltage which operates the memory array.

15. An integrated circuit as in claim 14 further comprising:

a write queue coupled to provide write data to the write data driver circuit.

16. An integrated circuit as in claim 1 wherein:

the write data signal driven onto the first complementary pair of global input bus lines is driven thereupon before the integrated circuit determines whether the memory cycle is a read cycle or a write cycle.

17. An integrated circuit as in claim 16 further comprising:

a first complementary pair of output bus lines associated with the first plurality of bit line pairs and separate from the first complementary pair of global input bus lines.

18. An integrated circuit as in claim 1 further comprising:

a second plurality of true and complement bit line pairs within the first array block located substantially adjacent as a group to the first plurality of true and complement bit line pairs;

a second plurality of bit line sense amplifiers, each coupled to a respective one of the second plurality of bit line pairs, and each responsive to the sense amplifier enable signal;

a second complementary pair of local bus lines associated with the second plurality of bit line sense amplifiers;

a second plurality of coupling circuits, each associated with a respective one of the second plurality of bit line sense amplifiers, each arranged to receive a differential write data signal on the second complementary pair of local bus lines and, when selected for writing, to communicate a corresponding differential write signal to the respective one of the second plurality of bit line sense amplifiers prior to latching the first and second plurality of bit line sense amplifiers;

wherein the first complementary pair of global input bus lines is also associated with the second plurality of bit line pairs; and

wherein the second coupling circuit is also arranged to communicate the differential write data signal received on the first complementary pair of global input bus lines to the second complementary pair of local bus lines.

19. An integrated circuit as in claim 1 wherein the first complementary pair of global input bus lines is implemented in an interconnect layer traversing generally overhead of the first plurality of true and complement bit line pairs.

20. An integrated circuit as in claim 19 wherein the first complementary pair of global input bus lines is implemented in the topmost interconnect layer.

21. An integrated circuit as in claim 1 further comprising:

a first equilibration circuit for equilibrating the first complementary pair of local bus lines together and to a bit line equilibrate voltage.

22. An integrated circuit as in claim 21 further comprising:

a second equilibration circuit for equilibrating the first complementary pair of global input bus lines together and to the bit line equilibrate voltage.

23. An integrated circuit including a dynamic memory array of individual memory cells organized as rows and columns, each row corresponding to one of a plurality of word lines and each column corresponding to one of a plurality of true and complement bit line pairs, a memory cell at a given row and column being coupled to the corresponding word line and coupled to either the true or complement corresponding bit line, said integrated circuit comprising:

a first array block including a first plurality of true and complement bit line pairs;

a first plurality of bit line sense amplifiers, each coupled to a respective one of the first plurality of bit line pairs, and each responsive to a sense amplifier enable signal;

a first complementary pair of bus lines associated with the first plurality of bit line pairs;

a first plurality of coupling circuits, each associated with a respective one of the first plurality of bit line sense amplifiers, each arranged to receive a differential write data signal on the first complementary pair of bus lines and, when selected for writing, to communicate, prior to latching the first plurality of bit line sense amplifiers, a corresponding differential write signal to the respective one of the first plurality of bit line sense amplifiers, which corresponding write signal substantially swallows a respective read signal otherwise developed as a result of accessing a respective memory cell; and

a sense amplifier enable control circuit for generating the sense amplifier enable signal for the first plurality of bit line sense amplifiers.

24. An integrated circuit as in claim 23 further comprising a processor.

25. An integrated circuit as in claim 23 wherein the first complementary pair of bus lines is arranged orthogonal to each of the first plurality of bit line pairs.

26. An integrated circuit as in claim 23 wherein:

the first complementary pair of bus lines is arranged parallel to each of the first plurality of bit line pairs; and

the first complementary pair of bus lines is further associated with a respective plurality of bit line pairs located within respective array blocks other than the first array block.

27. An integrated circuit as in claim 26 wherein:

the first complementary pair of bus lines is further associated with another plurality of bit line pairs located within the first array block.

28. An integrated circuit as in claim 23 wherein each of the first plurality of bit line sense amplifiers includes:

a true internal sense amplifier node and a complement internal sense amplifier node, together forming a complementary pair of internal sense amplifier nodes; and

a first pair of transistors respectively coupling the true and complement internal sense amplifier nodes to the true and complement bit lines of the respective one of the first plurality of bit line pairs;

wherein each respective one of the first plurality of coupling circuits is respectively coupled directly to the complementary pair of internal sense amplifier nodes of the respective one of the first plurality of bit line sense amplifiers.

29. An integrated circuit as in claim 23 wherein each respective one of the first plurality of coupling circuits is respectively coupled directly to the true and complement bit lines of a respective one of the first plurality of bit line pairs.

30. An integrated circuit as in claim 23 wherein the first complementary pair of bus lines comprises a unidirectional pair of global input bus lines.

31. An integrated circuit as in claim 23 wherein the first complementary pair of bus lines comprises a bi-directional pair of local input/output lines.

32. An integrated circuit as in claim 23 wherein, during a write cycle, a selected one of the first plurality of coupling circuits is turned on substantially before the first plurality of bit line sense amplifiers are enabled and begin to latch, and is turned off at approximately a time when the first plurality of bit line sense amplifiers are enabled and begin to latch.

33. An integrated circuit as in claim 23 further comprising a write queue.

34. An integrated circuit as in claim 23 further comprising:

a write data driver circuit coupled to the first complementary pair of bus lines for generating a differential write data signal thereupon which is of a magnitude substantially less than a rail-to-rail signal.

35. An integrated circuit as in claim 34 wherein the corresponding differential write signal communicated to the respective one of the first plurality of bit line sense amplifiers corresponds to a voltage change on each of the true and complement bit lines of the respective bit line pair, just prior to latching the bit line sense amplifiers and relative to a bit line equilibrate voltage, neither of which is substantially larger in magnitude than the greater of the voltage change on either a true or complement bit line, just prior to latching the bit line sense amplifiers and relative to the bit line equilibrate voltage, resulting from accessing a memory cell not being written.

36. An integrated circuit as in claim 35 wherein the corresponding differential write signal communicated to the respective one of the first plurality of bit line sense amplifiers comprises a differential signal whose magnitude, just prior to latching the bit line sense amplifiers, is not substantially less than a differential read signal within a bit line sense amplifier, just prior to latching the bit line sense amplifiers, resulting from accessing a memory cell not being written.

37. An integrated circuit including a dynamic memory array of individual memory cells organized as rows and columns, each row corresponding to one of a plurality of word lines and each column corresponding to one of a plurality of true and complement bit line pairs, a memory cell at a given row and column being coupled to the corresponding word line and coupled to either the true or complement corresponding bit line, said integrated circuit comprising:

a first array block including a first plurality of true and complement bit line pairs;

a first plurality of bit line sense amplifiers, each coupled to a respective one of the first plurality of bit line pairs, and each responsive to a sense amplifier enable signal;

a first complementary pair of bus lines associated with the first plurality of bit line pairs;

a first plurality of coupling circuits, each associated with a respective one of the first plurality of bit line sense amplifiers, each arranged to receive a differential write data signal on the first complementary pair of bus lines and, when selected for writing, to communicate a corresponding differential write signal to the respective one of the first plurality of bit line sense amplifiers prior to latching the first plurality of bit line sense amplifiers; and

a sense amplifier enable control circuit for generating the sense amplifier enable signal for the first plurality of bit line sense amplifiers at a time during a memory cycle substantially irrespective of whether the memory cycle is a read cycle or a write cycle.

38. An integrated circuit as in claim 37 further comprising a processor.

39. An integrated circuit as in claim 37 wherein the first complementary pair of bus lines is arranged orthogonal to each of the first plurality of bit line pairs.

40. An integrated circuit as in claim 37 wherein:

the first complementary pair of bus lines is arranged parallel to each of the first plurality of bit line pairs; and

the first complementary pair of bus lines is further associated with a respective plurality of bit line pairs located within respective array blocks other than the first array block.

41. An integrated circuit as in claim 40 wherein:

the first complementary pair of bus lines is further associated with another plurality of bit line pairs located within the first array block.

42. An integrated circuit as in claim 37 wherein each of the first plurality of bit line sense amplifiers includes:

a true internal sense amplifier node and a complement internal sense amplifier node, together forming a complementary pair of internal sense amplifier nodes; and

a first pair of transistors respectively coupling the true and complement internal sense amplifier nodes to the true and complement bit lines of the respective one of the first plurality of bit line pairs;

wherein each respective one of the first plurality of coupling circuits is respectively coupled directly to the complementary pair of internal sense amplifier nodes of the respective one of the first plurality of bit line sense amplifiers.

43. An integrated circuit as in claim 37 wherein each respective one of the first plurality of coupling circuits is respectively coupled directly to the true and complement bit lines of a respective one of the first plurality of bit line pairs.

44. An integrated circuit as in claim 37 wherein the first complementary pair of bus lines comprises a unidirectional pair of global input bus lines.

45. An integrated circuit as in claim 37 wherein the first complementary pair of bus lines comprises a bi-directional pair of local input/output lines.

46. An integrated circuit as in claim 37 wherein, during a write cycle, a selected one of the first plurality of coupling circuits is turned on substantially before the first plurality of bit line sense amplifiers are enabled and begin to latch, and is turned off at approximately a time when the first plurality of bit line sense amplifiers are enabled and begin to latch.

47. An integrated circuit as in claim 37 wherein:

the corresponding differential write signal coupled into a selected bit line sense amplifier, prior to latching the first plurality of bit line sense amplifiers, is of a magnitude substantially less than a rail-to-rail signal.

48. An integrated circuit as in claim 37 further comprising a write queue.

49. In an integrated circuit including a dynamic memory array, a method of operating the integrated circuit comprising:

enabling during a memory cycle a selected word line within an array block, thereby respectively coupling each memory cell associated with the selected word line to either a true or complement bit line of a respective complementary bit line pair;

coupling respectively each bit line pair within the array block to a respective bit line sense amplifier;

for a respective memory cell associated with the selected word line and which respective memory cell is to be written, developing a respective write signal within the respective bit line sense amplifier, said respective write signal substantially swallowing a respective read signal otherwise developed within the respective bit line sense amplifier as a result of accessing the respective memory cell; and

then

latching the bit line sense amplifiers within the array block, said latching accomplishing both restoring memory cells not written during the memory cycle and writing memory cells to be written during the memory cycle;

wherein a bit line pair not being written is disturbed by a neighboring bit line pair being written, prior to beginning to latch the bit line sense amplifiers, substantially no more than would occur if the neighboring bit line pair were not being written.

50. A method as in claim 49 wherein a respective write signal developed within the respective bit line sense amplifier corresponds to a voltage change on each of the true and complement bit lines of the respective bit line pair, just prior to latching the bit line sense amplifiers and relative to a bit line equilibrate voltage, neither of which is substantially larger in magnitude than the greater of the voltage change on either a true or complement bit line, just prior to latching the bit line sense amplifiers and relative to the bit line equilibrate voltage, resulting from accessing a memory cell not being written.

51. A method as in claim 50 wherein a respective write signal developed within a respective bit line sense amplifier comprises a differential signal whose magnitude, just prior to latching the bit line sense amplifiers, is not substantially less than a differential read signal within a bit line sense amplifier, just prior to latching the bit line sense amplifiers, resulting from accessing a memory cell not being written.

52. A method as in claim 51:

wherein the respective write signal developed within a respective bit line sense amplifier is developed by adding charge to one of the respective true and complement bit lines and by removing charge from the remaining one of the respective true and complement bit lines;

wherein even if charge read from the respective memory cell to be written subtracts from the respective write signal, the magnitude of the differential write signal developed within the respective bit line sense amplifier, just prior to latching the bit line sense amplifiers, is not substantially less than a differential read signal developed within a bit line sense amplifier, just prior to latching the bit line sense amplifiers, resulting from accessing a memory cell not being written; and

wherein even if charge read from the respective memory cell to be written adds to the respective write signal, the voltage change on each of the true and complement bit lines of the respective bit line pair, just prior to latching the bit line sense amplifiers and relative to a bit line equilibrate voltage, is not substantially larger in magnitude than the greater of the voltage change on either a true or complement bit line, just prior to latching the bit line sense amplifiers and relative to the bit line equilibrate voltage, resulting from accessing a memory cell not being written.

53. A method as in claim 52 wherein the magnitude of the respective write signal developed within a respective bit line sense amplifier, just prior to latching the bit line sense amplifiers, is substantially greater than a differential read signal within a bit line sense amplifier, just prior to latching the bit line sense amplifiers, resulting from accessing a memory cell not being written.

54. A method as in claim 49 wherein the respective write signal developed within a respective bit line sense amplifier is received from a write queue within the integrated circuit.

55. A method as in claim 54 wherein:

each respective write signal is conveyed to the respective bit line sense amplifier via a respective complementary pair of bus lines; and

a corresponding write data signal is already present on the respective complementary pair of bus lines before the integrated circuit determines whether the memory cycle is a write cycle.

56. A method as in claim 55 wherein the corresponding write data signal conveyed on each respective complementary pair of bus lines is received from the write queue within the integrated circuit and driven onto the respective complementary pair of bus lines at a time in which bit line pairs associated with memory cells coupled to the selected word line and not being written during the cycle are not significantly disturbed by capacitive coupling from voltage changes on the complementary pairs of bus lines.

57. A method as in claim 55 wherein a corresponding write data signal on a respective complementary pair of bus lines is of a magnitude substantially less than a rail-to-rail signal.

58. A method as in claim 57 wherein a corresponding write data signal on a respective complementary pair of bus lines comprises a dynamic signal which is capacitively maintained on the respective complementary pair of bus lines.

59. A method as in claim 58 wherein the capacitance of a respective bit line pair is much less than the capacitance of a respective complementary pair of bus lines.

60. A method as in claim 58 wherein the corresponding write data signal capacitively maintained on the respective complementary pair of bus lines is refreshed periodically until used to write a selected memory cell during a subsequent write cycle.

61. A method as in claim 49 employed in a dynamic memory array embedded within an integrated processor circuit.

62. In an integrated circuit including a dynamic memory array having individual memory cells organized as rows and columns, each row corresponding to one of a plurality of word lines and each column corresponding to one of a plurality of true and complement bit line pairs, a memory cell at a given row and column being coupled to the corresponding word line and coupled to either the true or complement corresponding bit line, a method of operating the integrated circuit comprising:

enabling, at a time during a memory cycle substantially irrespective of whether the memory cycle is a read cycle or a write cycle, a selected word line within an array block;

coupling respectively each bit line pair within the array block to an associated bit line sense amplifier;

enabling, if the memory cycle is a write cycle, a respective write circuit for each respective bit line pair having a respective memory cell to be written and which respective memory cell is coupled to the selected word line, said enabling to cause a respective write signal to develop within a respective bit line sense amplifier associated with the respective bit line pair in accordance with a respective write data signal, said respective write signal overcoming a respective read signal otherwise developed within each respective bit line sense amplifier to be written as a result of charge from each respective memory cell coupled to the selected word line being shared with its associated true or complement bit line of the respective bit line pair; and

then

latching, at a time during a memory cycle substantially irrespective of whether the memory cycle is a read cycle or a write cycle, the bit line sense amplifiers for all bit line pairs having a memory cell coupled to the selected word line, said latching accomplishing both restoring memory cells coupled to the selected word line and not written during the memory cycle and, if the memory cycle is a write cycle, writing memory cells to be written during the memory cycle.

63. A method as in claim 62 wherein during the memory cycle a bit line pair not being written is disturbed by a neighboring bit line pair being written, prior to beginning to latch the bit line sense amplifiers, substantially no more than would occur if the neighboring bit line pair were not being written.

64. A method as in claim 62 wherein each respective write signal, when developed within a respective bit line sense amplifier, results in a change of voltage on an individual bit line of a respective bit line pair, prior to latching the bit line sense amplifiers and relative to a bit line equilibrate voltage, whose magnitude is not substantially larger than a change of voltage on an individual bit line resulting from accessing a memory cell not being written.

65. A method as in claim 64 wherein each respective write signal, when developed within a respective bit line sense amplifier, results in a change of voltage on an individual bit line of a respective bit line pair, prior to latching the bit line sense amplifiers and relative to a bit line equilibrate voltage, which is approximately 200 mV or less in magnitude.

66. A method as in claim 62 wherein the respective write data signals are received from a write queue within the integrated circuit.

67. A method as in claim 66 wherein:

each respective write data signal is received by the respective write circuit via a respective complementary pair of bus lines; and

each respective write data signal is already present on the respective complementary pair of bus lines before the integrated circuit determines whether the memory cycle is a write cycle.

68. A method as in claim 67 wherein the respective write data signal conveyed on the respective complementary pair of bus lines is driven onto the respective complementary pair of bus lines at a time in which bit line pairs associated with memory cells coupled to the selected word line and not being written during the cycle are not substantially disturbed by capacitive coupling from voltage changes on the complementary pairs of bus lines.

69. A method as in claim 68 wherein the complementary pairs of bus lines are routed through the memory array using an interconnect layer above an interconnect layer used to implement the bit line pairs.

70. A method as in claim 68 wherein each respective complementary pair of bus lines is maintained with a respective write data signal at least until just after the bit line sense amplifiers have started sensing, and provided with a respective next write data signal, if at all, before bit line equilibration is substantially complete.

71. A method as in claim 62 wherein:

each respective write data signal is received by the respective write circuit via a respective complementary pair of bus lines; and

each respective write data signal, prior to latching the bit line sense amplifiers, is of a magnitude substantially less than a rail-to-rail signal.

72. A method as in claim 71 wherein the respective write data signal comprises a dynamic signal which is capacitively maintained on the respective complementary pair of bus lines.

73. A method as in claim 72 wherein each complementary pair of bus lines is substantially larger in capacitance than each bit line pair, so that in a write cycle a complementary pair of bus lines substantially swallows the read charge from the respective memory cell to be written coupled onto its associated true or complement bit line of the respective bit line pair.

74. A method as in claim 72 wherein the respective write data signal conveyed on each complementary pair of bus lines is refreshed periodically.

75. A method as in claim 74 wherein the respective write data signals are refreshed every N external clock cycles.

76. A method as in claim 74 wherein the respective write data signals are refreshed whenever a row refresh cycle is performed in a memory bank containing the array block.

77. A method as in claim 72 wherein the respective write data signal on each respective complementary pair of bus lines is generated by equilibrating the respective complementary pair of bus lines together and to a bit line equilibrate voltage, then coupling a substantially fixed amount of charge onto at least one bus line of the respective complementary pair of bus lines.

78. A method as in claim 77 wherein the respective write data signal on each respective complementary pair of bus lines is generated by equilibrating the respective complementary pair of bus lines together and to the bit line equilibrate voltage, then adding a substantially fixed amount of charge to one bus line of the respective complementary pair of bus lines and removing substantially an equal amount of charge from the other bus line of the respective complementary pair of bus lines.

79. A method as in claim 77 wherein the substantially fixed amount of charge is generated by a substantially fixed amount of current conducted for a substantially fixed amount of time.

80. A method as in claim 77 wherein the substantially fixed amount of charge is generated by a respective capacitor initially charged to a voltage and then coupled to at least one bus line of the respective complementary pair of bus lines.

81. A method as in claim 62 wherein:

each respective bit line sense amplifier includes a respective pair of array select transistors coupling the respective complementary pair of bit lines to respective complementary internal sense amplifier nodes; and

the array select transistors remain conductive both before and during latching the bit line sense amplifiers, substantially irrespective of whether the memory cycle is a read cycle or a write cycle.

82. A method as in claim 81 wherein:

each array select transistor is gated by a single array select signal in common; and

the array select signal, for a selected array block, is substantially irrespective of whether the memory cycle is a read cycle or a write cycle.

83. In an integrated circuit including a dynamic memory array having individual memory cells organized as rows and columns, each row corresponding to one of a plurality of word lines and each column corresponding to one of a plurality of true and complement bit line pairs, a memory cell at a given row and column being coupled to the corresponding word line and coupled to either the true or complement corresponding bit line, a method of operating the integrated circuit comprising:

generating a respective differential write data signal on respective complementary pairs of global input lines by driving, for each respective complementary pair of global input lines, one of said complementary pair of global input lines to a voltage substantially equal to a voltage that a memory cell, previously stored with a high level, would otherwise impart, if not written, onto a bit line coupled thereto, and driving the other of said complementary pair of global input lines to a voltage substantially equal to a voltage that a memory cell, previously stored with a low level, would otherwise impart, if not written, onto a bit line coupled thereto;

then

enabling a selected word line within an array block during a memory cycle; and

if the memory cycle is a write cycle, coupling each respective bit line pair having a memory cell which is to be written and which memory cell is coupled to the selected word line, to its respective complementary pair of global input lines so that each of the true and complement bit lines of the respective bit line pair being written is imparted with a change in voltage not substantially larger than that otherwise imparted by a memory cell, if not written, onto its associated true or complement bit line; and

then

latching the bit line sense amplifiers for all bit line pairs having a memory cell coupled to the selected word line, said latching accomplishing both restoring memory cells coupled to the selected word line and not written during the memory cycle and, if the memory cycle is a write cycle, writing memory cells to be written during the memory cycle;

whereby during the memory cycle, prior to beginning to latch the bit line sense amplifiers, a bit line pair not being written is disturbed by a neighboring bit line pair being written substantially no more than would occur if the neighboring bit line pair were not being written.

84. A method as in claim 83 further comprising:

if the memory cycle is a write cycle, turning off the coupling of a respective bit line pair to its associated complementary pair of global input lines before significantly latching its associated bit line sense amplifier.

85. A method as in claim 84 wherein after turning off the coupling during a write cycle, and before coupling again during the next write cycle:

the respective complementary pair of global input lines is equilibrated to a bit line equilibrate voltage; and

then

a respective write data signal is driven onto the respective pair of global input lines in preparation for the next write cycle.

86. A method as in claim 83 wherein the respective write data signal conveyed on a respective complementary pair of global input lines is received from a write queue within the integrated circuit.

87. A method as in claim 83 wherein the respective write data signal conveyed on a respective complementary pair of global input lines is driven onto the respective complementary pair of global input lines at a time in which bit line pairs associated with memory cells coupled to the selected word line and not being written during the cycle are not disturbed by capacitive coupling from voltage changes on the complementary pairs of global input lines.

88. A method as in claim 87 wherein each respective complementary pair of global input lines is maintained with a respective write data signal at least until just after the bit line sense amplifiers have started sensing, and provided with a respective next write data signal, if at all, before bit line equilibration is substantially complete.

89. A method as in claim 88 wherein the next write data signal is a regeneration of the write data signal previously conveyed on the respective complementary pair of global input lines, thereby accomplishing a refresh of the previous write data signal.

90. A method as in claim 88 wherein the next write data signal is driven in accordance with new write data to be written and is independent of the write data signal previously conveyed on the respective complementary pair of global input lines.

91. A method as in claim 83 wherein:

each respective bit line sense amplifier includes a respective pair of array select transistors coupling the respective complementary pair of bit lines to respective complementary internal sense amplifier nodes; and

the array select transistors remain conductive both before and during latching the bit line sense amplifiers, substantially irrespective of whether the memory cycle is a read cycle or a write cycle.

92. A method as in claim 83 wherein each respective write data signal comprises a dynamic signal which is capacitively maintained on the respective complementary pair of global input lines.

93. A method as in claim 92 wherein each complementary pair of global input lines is substantially larger in capacitance than each bit line pair, so that a complementary pair of global input lines substantially swallows the read charge from the respective memory cell coupled onto its associated true or complement bit line of the respective bit line pair.

94. A method as in claim 92 wherein the respective write data signal conveyed on a respective complementary pair of global input lines is refreshed periodically.

95. A method as in claim 94 wherein the respective write data signals are refreshed every N external clock cycles.

96. A method as in claim 94 wherein the respective write data signals are refreshed whenever a row refresh cycle is performed in a memory bank containing the array block.