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Dynamic memory array having write data applied to selected bit line sense amplifiers before sensing to write associated selected memory cells

  • US 6,212,109 B1
  • Filed: 08/11/1999
  • Issued: 04/03/2001
  • Est. Priority Date: 02/13/1999
  • Status: Expired due to Term
First Claim
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1. An integrated circuit including a dynamic memory array having individual memory cells organized as rows and columns, each row corresponding to one of a plurality of word lines and each column corresponding to one of a plurality of true and complement bit line pairs, a memory cell at a given row and column being coupled to the corresponding word line and coupled to either the true or complement corresponding bit line, said integrated circuit comprising:

  • a first array block including a first plurality of true and complement bit line pairs;

    a first plurality of bit line sense amplifiers, each coupled to a respective one of the first plurality of bit line pairs, and each responsive to a sense amplifier enable signal;

    a first complementary pair of local bus lines associated with the first plurality of bit line sense amplifiers;

    a first plurality of coupling circuits, each associated with a respective one of the first plurality of bit line sense amplifiers, each arranged to receive a differential write data signal on the first complementary pair of local bus lines and, when selected for writing, to communicate a corresponding differential write signal to the respective one of the first plurality of bit line sense amplifiers prior to latching the first plurality of bit line sense amplifiers;

    a first complementary pair of global input bus lines associated with the first plurality of bit line pairs and further associated with a respective plurality of bit line pairs located within respective array blocks other than the first array block;

    a second coupling circuit arranged to receive a differential write data signal on the first complementary pair of global input bus lines and to communicate the differential write data signal to the first complementary pair of local bus lines; and

    a sense amplifier enable control circuit for generating the sense amplifier enable signal for the first plurality of bit line sense amplifiers at a time during a memory cycle substantially irrespective of whether the memory cycle is a read cycle or a write cycle.

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