Test method for contacts in SRAM storage circuits

• US 6,212,115 B1
• Filed: 07/19/2000
• Issued: 04/03/2001
• Est. Priority Date: 07/19/2000
• Status: Expired due to Fees

• Current Assignee: Advanced Micro Devices SDN Berhad (Advanced Micro Devices, Inc.)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Jordan, Lewis
• Primary Examiner(s): Dinh, Son T.
• Application Number:
  US09/619,601
• Time in Patent Office: 258 Days
• Field of Search: 365/201, 714/27
• US Class Current: 365/201
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing

Abstract

A test system for SRAM uses two mechanical probes to contact the bit lines of a column of SRAM storage cells. A word line is selected and a voltage is applied through the first mechanical probe to the first bit line forcing the second and complementary bit line to have a conducting FET coupled via contacts and a section of the second bit line to the second mechanical probe. A variable voltage is applied to the second mechanical probe and the corresponding resulting currents are measured. The first and second mechanical probes are then reversed and the process repeated. The voltage versus current from the second mechanical probe determines electrical characteristics of the contacts of the SRAM bit cell. The resulting data determining the electrical characteristics of the SRAM contacts are used to control process parameters during manufacture, set process parameters during manufacturing development, and to aid in failure analysis of manufactured SRAM bit cells.

Claims

1. A method for determining characteristics of contacts in Static Random Access Memory (SRAM) circuits comprising the method steps of:

selecting a first word line of a particular row containing an SRAM storage circuit;

applying a voltage to a first bit line in a column containing said SRAM storage circuit;

applying a variable voltage to a corresponding first complement bit line of said first bit line in said column containing said SRAM storage circuit; and

varying said variable voltage over a voltage range while said selected first word line remains selected and measuring and recording the resulting current levels and corresponding variable voltage levels.

2. The method of claim 1, wherein each of said SRAM storage circuits comprises:

an SRAM storage cell, said SRAM storage cell comprising two cross-coupled inverters; and

bit line selection transistors.

3. The method of claim 1, further comprising the step of using said variable voltage and corresponding resulting currents to determine electrical characteristics of contacts in said SRAM storage circuits.

4. The method of claim 1, further comprising the step of isolating said first bit line and said first complement bit line from corresponding bit line pre-charge circuits and sense amplifier/write logic.

5. The method of claim 3, further comprising the step of using said electrical characteristics in determining process control parameters in an SRAM manufacturing line.

6. A test system for a Static Random Access Memory (SRAM), said test system comprising:

a first and a second test probe, said first probe operable to contact a first bit line and said second test probe operable to contact a first complement bit line;

a third test probe operable to contact and force a selected word line to a known state;

a voltage source coupled to said first test probe, said voltage source operable to force said first bit line associated with said selected word line to a known state;

a variable voltage coupled to said second test probe;

a current sense means operable to measure the current of said variable voltage; and

a storage circuit for storing voltage levels of said variable voltage and corresponding resulting current levels when said variable voltage is applied to SRAM storage circuits in said SRAM.

7. The test system of claim 6, wherein said SRAM storage circuits comprise:

an SRAM storage cell, said SRAM storage cell comprising two cross-coupled inverters; and

bit line selection transistors.

8. The test system of claim 6, wherein said variable voltage and said corresponding resulting currents are used to determine electrical characteristics of contacts in said SRAM storage circuits.

9. The test system of claim 6, wherein said first bit line and said first complement bit line are isolated from corresponding bit line pre-charge circuits and sense amplifier/write logic.

10. The test system of claim 8, wherein said electrical characteristics are used in determining process control parameters in an SRAM manufacturing line.

11. A process control system for a SRAM manufacturing line comprising:

a wafer or packaged unit handling system for placing an SRAM wafer or packaged unit in a test station;

an alignment system for aligning test probes to SRAM storage circuits;

an SRAM measurement system, said SRAM measurement system further comprising;

a first and a second test probe, said first probe operable to contact a first bit line and said second test probe operable to contact a first complement bit line;

a third test probe operable to contact and force a selected word line to a known state;

a voltage source coupled to said first test probe, said voltage source operable to force said first bit line associated with said selected word line to a known state;

a variable voltage coupled to said second test probe;

a current sense means operable to measure the current of said variable voltage; and

a storage circuit for storing voltage levels of said variable voltage and corresponding resulting current levels when said variable voltage is applied to said SRAM storage circuits.

12. The process control system of claim 11, wherein each of said SRAM storage circuits comprises:

an SRAM storage cell, said SRAM storage cell comprising two cross-coupled inverters; and

bit line selection transistors.

13. The process control system of claim 11, wherein said variable voltage and said corresponding resulting currents are used to determine electrical characteristics of contacts in said SRAM storage circuits.

14. The process control system of claim 11, wherein said first bit line and said first complement bit line are isolated from corresponding bit line pre-charge circuits and sense amplifier/write logic.

15. The process control system of claim 13, wherein said electrical characteristics of contacts are used in determining process control parameters in an SRAM manufacturing line.