Full-duplex speakerphone circuit including a control interface

• US 6,212,273 B1
• Filed: 03/20/1998
• Issued: 04/03/2001
• Est. Priority Date: 03/20/1998
• Status: Expired due to Term

• Current Assignee: Crystal Semiconductor Corporation (Cirrus Logic Incorporated)
• Original Assignee: Crystal Semiconductor Corporation (Cirrus Logic Incorporated)
• Inventors: Wilson, Brent W., Hemkumar, Nariankadu D.
• Primary Examiner(s): Chan, Wing F.
• Application Number:
  US09/045,735
• Time in Patent Office: 1,110 Days
• Field of Search: 379/387-392, 379/406-411, 379/420
• US Class Current: 379/406.08
• CPC Class Codes: H03G 3/3005 in amplifiers suitable for low-frequencies, e.g. audio amplifiers H03G3/32, H03G3/34 take precedence
• CPC Class Codes: H03G 3/3089 Control of digital or coded signals
• CPC Class Codes: H04M 1/20 Arrangements for preventing acoustic feed-back H04M1/62 takes precedence
• CPC Class Codes: H04M 9/082 using echo cancellers echo cancellers per se H04B3/23

Abstract

A full-duplex communication device includes a transmit channel, a receive channel, and echo cancellers connected between the transmit channel and the receive channel. A plurality of control parameters and status indicators are defined for both channels. The plurality of control parameters are accessed via a writable interface for controlling operations of the communication device. Typically the control parameters are modified, enabled, and disabled based on an implemented control method and based on signal conditions, including noise, echo, tone, and other abnormal noise conditions. A writable access port enables a user to request tweaking, modification, enabling, and disabling of multiple features and controls. A readable/writable access port enables access to multiple status parameters that are indicative of the status of the communication device and channel operating conditions.

Claims

1. A full-duplex communication circuit comprising:

a signal path;

a half-duplex controller coupled to the signal path;

a writable access port;

a controller interface coupled to the access port and coupled to the half-duplex controller, the controller interface including a writable register, the writable register including a half-duplex mode enable/disable field, the half-duplex mode enable/disable field controlling the half-duplex controller to enable and disable half-duplex mode operation.

2. A circuit according to claim 1, further comprising:

a receive signal path;

a receive half-duplex controller coupled to the receive signal path;

a transmit signal path;

a transmit half-duplex controller coupled to the transmit signal path; and

an adaptive filter coupled to the transmit signal path and coupled to the receive signal path for accessing a first signal, determining a compensation signal from the first signal, and compensating a second signal using the compensating signal to form a compensated second signal having a loop gain reduction;

wherein the controller interface enables half-duplex mode operation so that the circuit operates in half-duplex mode if the echo canceller does not supply sufficient loop gain reduction to prevent howling, and the controller interface disables half-duplex mode operation to prevent half- duplex mode operation.

3. A circuit according to claim 1, further comprising:

a suppressor coupled to the signal path;

a controller interface coupled to the access port and coupled to the suppressor, the controller interface including a writable register, the writable register including a suppressor threshold field, the suppressor threshold field controlling the suppressor to set a speech detection threshold for disengaging suppression.

4. A circuit according to claim 1, wherein:

the controller interface writable register includes a half-duplex holdover delay field, the half-duplex holdover delay field setting a delay time during which a change of channel ownership is delayed to prevent false switching due to the presence of echoes.

5. A circuit according to claim 1, further comprising:

an instability detector coupled to the half-duplex controller, the instability detector detecting an instability condition and responding to the instability detection by transitioning into the half-duplex mode operation when enabled;

wherein the controller interface writable register includes a howling detector enable/disable field for enabling and disabling the instability detector.

6. A circuit according to claim 1, wherein:

a suppressor coupled to the signal path;

a controller interface coupled to the access port and coupled to the suppressor, the controller interface including a writable register, the writable register including a double talk suppression disengage ramp rate field controlling the suppressor rate at which suppression attenuation returns to 0 dB on cessation of double talk.

7. A circuit according to claim 1, wherein:

a suppressor coupled to the signal path;

a controller interface coupled to the access port and coupled to the suppressor, the controller interface including a writable register, the writable register including a suppressor threshold field, the suppressor threshold field controlling the suppressor to set a speech detection threshold for disengaging suppression; and

the writable register further including a double talk suppression disengage ramp rate field controlling the suppressor rate at which suppression attenuation returns to 0 dB on cessation of double talk.

8. A circuit according to claim 1, wherein:

a suppressor coupled to the signal path;

a controller interface coupled to the access port and coupled to the suppressor, the controller interface including a writable register, the writable register including a suppression attenuation field controlling the amount of suppression attenuation inserted into a signal path when suppression is engaged in the signal path.

9. A circuit according to claim 8, wherein:

the suppression attenuation field is a transmit attenuation field controlling the amount of suppression attenuation inserted into the transmit signal path.

10. A circuit according to claim 8, wherein:

the suppression attenuation field is a receive attenuation field controlling the amount of suppression attenuation inserted into the receive signal path.

11. A circuit according to claim 1, wherein:

the writable register includes a transmit half-duplex detection threshold field for selectively setting a threshold for detecting speech so that speech is occurring in the transmit channel when the transmit channel signal power exceeds the transmit channel signal power.

12. A circuit according to claim 1, wherein:

the writable register includes a receive half-duplex detection threshold field for selectively setting a threshold for detecting speech so that speech is occurring in the receive channel when the receive channel signal power exceeds the receive channel signal power.

13. A circuit according to claim 1, wherein:

the writable register includes an idle state control field for selectively determining whether the receive channel or the transmit channel is idle while operating in the half-duplex mode.

14. A fill-duplex communication circuit comprising:

a signal path;

a suppressor coupled to the signal path;

a writable access port;

a controller interface coupled to the access port and coupled to the suppressor, the controller interface including a writable register, the writable register including a suppressor threshold field, the suppressor threshold field controlling the suppressor to set a speech detection threshold for disengaging suppression.

15. A circuit according to claim 14, wherein:

the suppressor threshold field sets a speech detection threshold for disengaging suppression in the signal path, suppression being inserted into the signal path unless a detected input signal to the signal path exceeds a channel noise power by the inserted suppression so that speech is assumed to be detected and suppression is defeated until speech is no longer detected.

16. A circuit according to claim 14, further comprising:

a transmit signal path;

a transmit suppressor coupled to the transmit signal path;

a receive signal path; and

a receive suppressor coupled to the receive signal path;

wherein the controller interface includes a writable register including a transmit suppressor threshold field and a receive suppressor threshold field, the transmit suppressor threshold field and the receive suppressor threshold field controlling the transmit suppressor and the receive suppressor, respectively, to set a speech detection threshold for disengaging suppression.

17. A full-duplex communication circuit comprising:

a signal path;

a suppressor coupled to the signal path;

a writable access port;

a controller interface coupled to the access port and coupled to the suppressor, the controller interface including a writable register, the writable register including a double talk suppression disengage ramp rate field controlling the suppressor rate at which suppression attenuation returns to 0 dB on cessation of double talk.

18. A circuit according to claim 17, wherein:

the writable register includes a suppressor threshold field, the suppressor threshold field controlling the suppressor to set a speech detection threshold for disengaging suppression.

19. A circuit according to claim 18, wherein:

the suppressor threshold field sets a speech detection threshold for disengaging suppression in the signal path, suppression being inserted into the signal path unless a detected input signal to the signal path exceeds a channel noise power by the inserted suppression so that speech is assumed to be detected and suppression is defeated until speech is no longer detected.

20. A circuit according to claim 17, wherein:

the writable register includes fields controlling a transmit suppression parameter in the transmit signal path.

21. A circuit according to claim 17, wherein:

the writable register includes fields controlling a receive suppression parameter in the receive signal path.

22. A circuit according to claim 17, wherein:

the writable register includes a supplementary echo suppressor enable/disable field for selectively enabling and disabling echo suppression in the signal path.

23. A circuit according to claim 17, wherein:

the writable register includes a supplementary echo suppressor threshold field for selectively setting an ERLE threshold for discriminating between echo and speech by the suppressor.

24. A circuit according to claim 17, wherein:

the writable register includes a suppression attenuation field controlling the suppression attenuation inserted into the signal path when suppression is engaged.

25. A circuit according to claim 17, wherein:

the writable register includes a suppression bias field for controlling the facility with which a speaker disengages and maintains disengagement of suppression.

26. A circuit according to claim 17, wherein:

the writable register includes a supplementary echo suppressor mode enable/disable field for selectively setting a suppressor mode to a default_on mode and a default_off mode.

27. A circuit according to claim 17, further comprising:

a transmit signal path;

a receive signal path; and

a double talk detector for detecting simultaneous speech in the transmit signal path and the receive signal path;

wherein the writable register includes a double talk suppression disengage ramp rate field for controlling the rate attenuation returns to 0 dB upon cessation of double talk.

28. A circuit according to claim 17, further comprising:

a transmit signal path;

a receive signal path; and

a double talk detector for detecting simultaneous speech in the transmit signal path and the receive signal path;

wherein the writable register includes a double talk suppression attenuation field for controlling attenuation of the suppressor when an operating state is determined to be a double-talk state in which both channels are simultaneously active.

29. A circuit according to claim 17, further comprising:

a transmit signal path;

a receive signal path; and

an echo path absence and presence detector coupled to the transmit signal path and the receive signal path for detecting the absence or presence of an echo path;

wherein the writable register includes an echo path detector disable/enable field.

30. A circuit according to claim 29, further comprising:

a transmit channel echo path absence and presence detector; and

a receive channel echo path absence and presence detector;

wherein the writable register includes a transmit channel echo path detector disable/enable field and a receive channel echo path detector disable/enable field.

31. A full-duplex communication circuit comprising:

a receive signal path;

a receive half-duplex controller coupled to the receive signal path;

a transmit signal path;

a transmit half-duplex controller coupled to the transmit signal path; and

an echo canceller including an adaptive filter coupled to the transmit signal path and coupled to the receive signal path for accessing a first signal, determining a compensation signal from the first signal, and compensating a second signal using the compensating signal to form a compensated second signal having a loop gain reduction;

a writable access port;

a controller interface coupled to the access port and coupled to the half-duplex controller, the controller interface including a writable register having a field for controlling operation of the adaptive filter.

32. A circuit according to claim 31, wherein:

the writable register includes a control adaptive filter coefficients field for controlling adaptive filter coefficients of the echo canceller.

33. A circuit according to claim 31, wherein:

the writable register includes a control adaptive filter coefficients field for controlling adaptive filter coefficients of the echo canceller to adjust an echo path to cancel echo.

34. A circuit according to claim 31, wherein:

the writable register includes a control adaptive filter coefficients field for controlling adaptive filter coefficients of the echo canceller to disable the echo canceller.

35. A circuit according to claim 31, wherein:

the writable register includes a control adaptive filter coefficients field for controlling adaptive filter coefficients of the echo canceller to hold the adaptive filter coefficients to current values, thereby freezing the echo canceller.

36. A circuit according to claim 31, wherein:

the writable register includes a control adaptive filter coefficients field for controlling adaptive filter coefficients of a transmit echo canceller for canceling echoes in the transmit signal path.

37. A circuit according to claim 31, wherein:

the writable register includes a control adaptive filter coefficients field for controlling adaptive filter coefficients of a receive echo canceller for canceling echoes in the receive signal path.

38. A circuit according to claim 31, further comprising:

an acoustic echo canceller for canceling echoes in an acoustic echo path;

a network echo canceller for canceling echoes in a network echo path;

wherein the writable register includes a control adaptive filter coefficients field for selectively allocating a plurality of adaptive filter coefficients between the acoustic echo canceller and the network echo canceller.

39. A circuit according to claim 31, wherein:

the writable register includes a control adaptive filter coefficients field for controlling timing of an exponential decay of acoustic echoes.

40. A circuit according to claim 31, wherein:

the writable register includes a control adaptive filter coefficients field for controlling convergence speed of a decay rate of acoustic echoes.

41. A circuit according to claim 31, wherein:

the writable register includes a control adaptive filter coefficients field for controlling timing of an exponential decay of acoustic echoes so that initial taps in the adaptive filter are large and later taps are small allowing initial taps to adapt faster and later taps to maintain stability.

42. A circuit according to claim 31, wherein:

the writable register includes a control adaptive filter coefficients field for controlling ERLE threshold so that full-duplex operation is allowed only when the current ERLE exceeds the ERLE threshold.

43. A circuit according to claim 31, wherein:

the writable register includes a noise threshold field for setting a noise threshold for detection of existence or nonexistence of an echo path and for determining whether full-duplex operation is allowed.

44. A circuit according to claim 31, further comprising:

a path change detector coupled to the transmit signal path and the receive signal path, wherein;

the writable register includes an ec ho canceller path change enable/disable field for disabling of a path change detection operation to allow testing of a double talk detector when a path change detector is disabled from transitioning into half-duplex mode.

45. A circuit according to claim 31, further comprising:

a path change detector coupled to the transmit signal path and the receive signal path, wherein;

the writable register includes an path change sensitivity selection field for determining sensitivity of the path change detector.

46. A circuit according to claim 31, further comprising:

an analog-to-digital converter (ADC) coupled to a signal path of the transmit signal path and the receive signal path;

a digital-to-analog converter (DAC) coupled to the signal path; and

the writeable register includes a side tone field for adding digital on-chip sidetone to the ADC output signal that is generated by attenuation of the DAC input signal.

47. A circuit according to claim 31, further comprising:

a tone detector coupled to a signal path of the receive signal path and the transmit signal path; and

the writeable register includes a tone detect enable/disable field for selectively enabling and disabling the tone detector.

48. A circuit according to claim 31, further comprising:

a pre-emphasis filter coupled to the echo canceller and coupled to a signal path of the receive signal path and the transmit signal path; and

the writeable register includes a pre-emphasis filter enable/disable field for selectively enabling and disabling the pre-emphasis filter.

49. A full-duplex communication circuit comprising:

a signal path;

a programmable analog gain stage amplifier coupled to the signal path;

a writable access port;

a controller interface coupled to the access port and coupled to the programmable analog gain stage amplifier, the controller interface including a writable register, the writable register including a parameter for controlling the programmable analog gain stage amplifier.

50. A circuit according to claim 49, wherein:

the writable register includes an analog gain select field for controlling the amount of additional on-chip analog gain that is supplied to the acoustic input of the full-duplex speakerphone circuit by the programmable analog gain stage amplifier.

51. A circuit according to claim 49, wherein:

the writable register includes an analog gain enable/disable field for selectively enabling and disabling automatic gain control of the programmable analog gain stage amplifier.

52. A circuit according to claim 49, wherein:

the writable register includes a volume control field for controlling the signal volume in the signal path.

53. A full-duplex communication circuit comprising:

a receive signal path;

a transmit signal path; and

an echo canceller including an adaptive filter coupled to the transmit signal path and coupled to the receive signal path for accessing a first signal, determining a compensation signal from the first signal, and compensating a second signal using the compensating signal to form a compensated second signal having a loop gain reduction;

a readable access port;

a controller interface coupled to the readable access port and coupled to the half-duplex controller, the controller interface including a readable register having a field reporting a circuit status.

54. A circuit according to claim 53, further comprising:

a receive half-duplex controller coupled to the receive signal path;

a transmit half-duplex controller coupled to the transmit signal path; and

the readable register includes a HDX/FDX status field for reporting whether the circuit is operating in a half-duplex mode or a full-duplex mode.

55. A circuit according to claim 53, further comprising:

a receive half-duplex controller coupled to the receive signal path;

a transmit half-duplex controller coupled to the transmit signal path; and

the readable register includes a HDX channel ownership status field for reporting whether the receive signal path or the transmit signal path is active while operating in the half-duplex mode.

56. A circuit according to claim 53, further comprising:

a receive speech detector coupled to the receive signal path;

a transmit speech detector coupled to the transmit signal path; and

the readable register includes a receive speech detection and a transmit speech detection status field for reporting whether a speech signal is active on the receive signal path and a speech signal is active on the transmit signal path.

57. A circuit according to claim 53, further comprising:

an ERLE calculator for calculating a current ERLE value;

a comparator for determining a best ERLE value on the basis of a current ERLE values calculated over time; and

the readable register includes a best ERLE value field and a current ERLE value field for reporting a best ERLE value and a current ERLE value.

58. A circuit according to claim 53, further comprising:

a power estimator coupled to the receive signal path and the transmit signal path;

a noise estimator coupled to the power estimator for determining a noise estimate; and

the readable register includes a noise field for reporting a noise estimate.

59. A circuit according to claim 53, further comprising:

a gain stage amplifier coupled to a signal path of the receive signal path and the transmit signal path, the gain stage amplifier controlled by an automatic gain parameter; and

the readable register includes an automatic gain control status field for reporting the automatic gain parameter.

60. A circuit according to claim 53, further comprising:

a receive suppressor coupled to the receive signal path;

a transmit suppressor coupled to the transmit signal path; and

the readable register includes a suppressor status field for reporting whether the transmit suppressor and the receive suppressor are engaged.

61. A circuit according to claim 53, further comprising:

an echo canceller including an adaptive filter coupled to the transmit signal path and coupled to the receive signal path for accessing a first signal, determining a compensation signal from the first signal, and compensating a second signal using the compensating signal to form a compensated second signal having a loop gain reduction; and

the readable register includes an echo canceller status field for reporting an echo canceller status.

62. A circuit according to claim 53, further comprising:

a tone detector coupled to a signal path of the receive signal path and the transmit signal path; and

the readable register includes a tone detect status field for reporting whether a tone is detected in the signal path.

63. A circuit according to claim 53, further comprising:

an analog-to-digital converter (ADC) coupled to a signal path of the receive signal path and the transmit signal path; and

the readable register includes an ADC clip detect status field for reporting whether a signal is clipped by the ADC.