Merged variable gain mixers

• US 6,212,369 B1
• Filed: 06/05/1998
• Issued: 04/03/2001
• Est. Priority Date: 06/05/1998
• Status: Expired due to Term

• Current Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Original Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Inventors: Avasarala, Madhu
• Primary Examiner(s): Tsang, Fan
• Assistant Examiner(s): Ferguson, Keith
• Application Number:
  US09/092,808
• Time in Patent Office: 1,033 Days
• Field of Search: 455/333, 455/323, 455/326, 455/209, 455/253.2, 455/293, 455/315, 455/550, 455/403, 327/256, 327/356, 327/359, 327/358, 327/355, 327/560, 327/346
• US Class Current: 455/333
• CPC Class Codes: H03D 2200/0025 Gain control circuits
• CPC Class Codes: H03D 2200/0047 Offset of DC voltage or frequency
• CPC Class Codes: H03D 2200/0084 Lowering the supply voltage and saving power
• CPC Class Codes: H03D 2200/0088 Reduction of intermodulation, nonlinearities, adjacent channel interference; intercept points of harmonics or intermodulation products
• CPC Class Codes: H03D 7/1425 with transistors
• CPC Class Codes: H03D 7/1433 using bipolar transistors H03D7/145 takes precedence
• CPC Class Codes: H03D 7/1441 using field-effect transistors H03D7/145 takes precedence
• CPC Class Codes: H03D 7/1458 Double balanced arrangements, i.e. where both input signals are differential
• CPC Class Codes: H03G 1/0023 in emitter-coupled or cascode amplifiers H03G1/0029 takes precedence

Abstract

The present invention teaches parallel coupling what are herein termed a “switching stage” and a “steering stage,” thereby arranging the mixer and variable gain amplifier circuitry as a single merged circuit. The merged variable gain mixers of the present invention provide mixing and gain functionality utilizing only that power needed for a basic mixer function and only the transconductance of the basic mixer function (thereby eliminating non-linearities introduced by additional transconductance stages of prior art circuitry). Further, in the merged variable gain mixers described herein, no additional headroom is needed other than what is required by the basic mixer function. The present invention contemplates a variety of merged variable gain mixers including AC and DC coupled merged variable gain mixer of both single and double balanced configuration.

Claims

1. A merged variable gain mixer comprising:

a switching device having first and second input pairs and an output pair, the switching device responsive to a signal LO applied to the first input pair and an input signal I_f applied to the second input pair to generate an output signal O_f at the output pair, the output signal O_f having an amplitude that is a function of the input signal I_f and an output frequency that is a function of both the signal LO and the input signal I_f; and

a current steering device having a first input pair, a supply voltage input, and a control voltage input, the current steering device operable to control, as a function of a control voltage V_gc applied at the control voltage input, current flowing between a supply voltage V_cc coupled to the supply voltage input and the current steering device first input pair,

wherein the switching device second input pair and the current steering device first input pair are coupled together such that the current steering device can attenuate the output signal O_f by steering a portion of the current of the input signal I_f away from the switching device and dumping that portion of the current out to the supply voltage V_cc.

2. A merged variable gain mixer as recited in claim 1, wherein the switching device includes four transistors Q1, Q2, Q3, and Q4, the bases of transistors Q1 and Q2 coupled to a first terminal of the switching device first input pair, the bases of transistors Q3 and Q4 coupled to a second terminal of the switching device first input pair, the emitters of transistors Q1 and Q3 coupled to a first terminal of the switching device second input pair, the emitters of transistors Q2 and Q4 coupled to a second terminal of the switching device second pair, the collectors of transistors Q1 and Q4 coupled to a first terminal of the switching device output pair, and the collectors of transistors Q2 and Q3 coupled to a second terminal of the switching device output pair.

3. A merged variable gain mixer as recited in claim 2 wherein the four transistors Q1, Q2, Q3, and Q4 are bipolar transistors.

4. A merged variable gain mixer as recited in claim 2 wherein the four transistors Q1, Q2, Q3, and Q4 are field-effect transistors.

5. A merged variable gain mixer as recited in claim 2, wherein the current steering device further includes a second input pair coupled to the switching device first input pair.

6. A merged variable gain mixer as recited in claim 2 wherein the current steering device includes four transistors Q5, Q6, Q7, and Q8, the bases of transistors Q5 and Q8 being coupled to the first terminal of the switching device first input pair, the bases of transistors Q5 and Q8 further coupled to the control voltage input through a resistor R₁, the base of Q6 coupled to the control voltage input through a resistor R₂, the base of Q7 coupled to the control voltage input through a resistor R₃, the collectors of transistors Q5, Q6, Q7, and Q8 coupled together at the supply voltage input, the emitters of transistors Q5 and Q6 coupled together at the first terminal of the switching device second input pair, and the emitters of transistors Q7 and Q8 coupled together at the second terminal of the switching device second input pair.

7. A merged variable gain mixer as recited in claim 6 wherein the four transistors Q5, Q6, Q7, and Q8 are bipolar transistors.

8. A merged variable gain mixer as recited in claim 6 wherein the four transistors Q5, Q6, Q7, and Q8 are field-effect transistors.

9. A merged variable gain mixer having a double balanced configuration, the merged variable gain mixer comprising:

a mixing quad having four transistors Q1, Q2, Q3, and Q4, the bases of transistors Q1 and Q2 coupled to a first terminal, the bases of transistors Q3 and Q4 coupled to a second terminal, the emitters of transistors Q1 and Q3 coupled to a third terminal, the emitters of transistors Q2 and Q4 coupled to a fourth terminal, the collectors of transistors Q1 and Q4 coupled to a fifth terminal, and the collectors of transistors Q2 and Q3 coupled to a sixth terminal; and

a Gilbert current steering quad having four transistors Q5, Q6, Q7, and Q8, the bases of transistors Q5 and Q8 being coupled to a seventh terminal, the bases of transistors Q5 and Q8 further coupled to a control voltage input through a resistor R₁, the base of Q6 coupled to the control voltage input through a resistor R₂, the base of Q7 coupled to the control voltage input through a resistor R₃, the collectors of transistors Q5, Q6, Q7, and Q8 coupled together at a supply voltage input, the emitters of transistors Q5 and Q6 coupled together at the third terminal, and the emitters of transistors Q7 and Q8 coupled together at the third terminal.

10. A merged variable gain mixer as recited in claim 9 further comprising a first blocking capacitor intended to electrically couple the first terminal to a first local oscillator terminal and a second blocking capacitor intended to electrically couple the second terminal to a second local oscillator terminal.

11. A merged variable gain mixer as recited in claim 10 further comprising a third blocking capacitor intended to electrically couple the seventh terminal to the first local oscillator terminal and a fourth blocking capacitor intended to electrically couple the bases of transistors Q6 and Q7 to the second local oscillator terminal.

12. A merged variable gain mixer as recited in claim 9 wherein the transistors are bipolar transistors.

13. A merged variable gain mixer as recited in claim 9 wherein the transistors are field-effect transistors.

14. A merged variable gain mixer as recited in claim 9 further comprising a bias device capable of providing bias signals at the bases of the transistors Q1, Q2, Q3, and Q4.

15. A merged variable gain mixer as recited in claim 14 wherein the bias device has a bias voltage V_b, and a resistor R₅ coupling the bias voltage V_b to the bases of transistors Q1 and Q2 and a resistor R₆ coupling the bias voltage V_b to the bases of transistors Q3 and Q4.

16. A merged variable gain mixer having a single balanced configuration, the merged variable gain mixer comprising:

a mixing stage having two transistors Q1 and Q2; and

a current steering stage having two transistors Q3 and Q4,

wherein the mixing stage and the current steering stage are coupled in parallel, the emitters of the transistors Q1, Q2, Q3 and Q4 being coupled together forming a current input terminal, the collectors of Q3 and Q4 being coupled together at a supply voltage input, and the collectors of the transistors Q1 and Q2 forming output terminals,

wherein the merged variable gain mixer arranged for use as an AC coupled merged variable gain mixer, the bases of the transistors Q1 and Q2 being provided a DC bias and further coupled to a local oscillator signal through a pair of DC blocking capacitors, the bases of the transistors Q3 and Q4 being provided a DC bias and a control signal suitable for controlling the gain of the variable gain mixer.

17. A merged variable gain mixer as recited in claim 16 wherein the transistors Q1, Q2, Q3 and Q4 are bipolar transistors.

18. A merged variable gain mixer as recited in claim 16 wherein the transistors Q1, Q2, Q3, and Q4 are field-effect transistors.

19. A merged variable gain mixer having a single balanced configuration, the merged variable gain mixer comprising:

a mixing stage having two transistors Q1 and Q2; and

a current steering stage having two transistors Q3 and Q4,

wherein the mixing stage and the current steering stage are coupled in parallel, the emitters of the transistors Q1, Q2, Q3 and Q4 being coupled together forming a current input terminal, the collectors of Q3 and Q4 being coupled together at a supply voltage input, and the collectors of the transistors Q1 and Q2 forming output termninals,

wherein the merged variable gain mixer arranged for use as a DC coupled merged variable gain mixer switched by a local oscillator signal LO composed of differential parts LO1 and LO2, the local oscillator signal LO including DC bias and a gain control signal, the bases of Q1 and Q2 being differentially coupled to LO1 and the bases of the transistors Q3 and Q4 being differentially coupled to LO2.

20. A method for mixing a variably amplifying an input signal I_f in order to generate an output signal O_f, the method comprising the acts of:

receiving an input signal I_f having an input frequency and an input current;

receiving a local oscillator signal;

receiving a gain control voltage V_gc;

absorbing a portion of the input current as a function of the gain control voltage V_gc and the local oscillator signal, thereby generating an attenuated input signal having an attenuated input current; and

generating an output signal O_f that is a function of the attenuated input signal, the input frequency, and the local oscillator signal,

wherein the control voltage V_gc can be selected such that the attenuated input current is substantially equivalent to the input current.

21. A method for mixing a variably amplifying an input signal I_f in order to generate an output signal O_f, the method comprising the acts of:

receiving an input signal I_f having an input frequency and an input current;

receiving a local oscillator signal;

receiving a gain control voltage V_gc;

absorbing a portion of the input current as a function of the gain control voltage V_gc and the local oscillator signal, thereby generating an attenuated input signal having an attenuated input current; and

generating an output signal O_f that is a function of the attenuated input signal, the input frequency, and the local oscillator signal,

wherein the act of generating an output signal O_f includes amplifying the attenuated input current by a constant value.

22. A method as recited in claim 21 wherein the constant value is unity.

23. A method as recited in claim 21 wherein the constant value is greater than unity.