Altering thread priorities in a multithreaded processor

• US 6,212,544 B1
• Filed: 10/23/1997
• Issued: 04/03/2001
• Est. Priority Date: 10/23/1997
• Status: Expired due to Term

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Wottreng, Andrew Henry, Borkenhagen, John Michael, Flynn, William Thomas
• Primary Examiner(s): Banankhah, Majid A.
• Application Number:
  US08/958,718
• Time in Patent Office: 1,258 Days
• Field of Search: 709/101, 709/102, 709/103, 709/104, 709/100, 709/108
• US Class Current: 718/103
• CPC Class Codes: G06F 9/3009 Thread control instructions
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/4843 by program, e.g. task dispatcher, supervisor, operating system

Abstract

A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread switch will occur. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive unproductive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager capable of changing the priority of the different threads and thus superseding thread switch events.

Claims

1. A method of computer processing, comprising:

(a) executing at least one of a plurality of threads of instructions in a multithreaded processor, each of said plurality of threads having a priority bit; and

(b) altering the relative priority bit of one of said plurality of threads using either or both a thread switch event experienced by said one of said plurality of threads and an instruction executed by said processor;

(c) determining the applicability of a plurality of hardware thread switch conditions that affect when said multithreaded processor switches threads.

2. The method of claim 1, further comprising:

(d) switching from one of the plurality of threads to another of the plurality based on the priority bit of each thread.

3. The method of claim 1, wherein a signal generated by hardware alters the priority bit of one or more threads.

4. The method of claim 3, wherein the signal results from an event external to the multithreaded processor.

5. The method of claim 1, wherein a thread switch manager alters the priority bit of one or more threads.

6. The method of claim 1, wherein the priority of one of the plurality of threads is higher than another of the plurality of threads.

7. The method of claim 1, wherein at least two of the plurality of threads can have equal priority.

8. The method of claim 1, wherein the priority of any of the plurality of threads can be high, medium, or low.

9. The method of claim 2, wherein switching from a first of the plurality of threads to a second of the plurality occurs when the first thread has a lower priority than the second thread and the second thread is in a ready state.

10. The method of claim 1, wherein switching from the one of the plurality of threads having a higher priority than another of the plurality of threads is disabled for one of said plurality of hardware thread switch conditions.

11. A method of computer processing, comprising:

(a) executing at least one of a plurality of threads of instructions in a multithreaded processor, each of the threads having a priority bit in a thread state register in said multithreaded processor;

(b) altering the priority bit of one or more of the plurality of threads using a thread switch manager;

(c) switching execution from a first of the plurality of threads to a second of the plurality of threads if the first thread has a lower priority than the second thread and the second thread is in a ready state;

(d) not switching execution from the one of the plurality of threads based on the relative priority of said plurality of threads despite the occurrence of thread switch events which would otherwise cause a thread switch as determined by hardware thread switch conditions.

12. A thread switch manager for a computer processing system, comprising:

a multithreaded processor;

a plurality of threads of instructions comprising at least one active thread in the multithreaded processor;

at least one priority switch instruction;

at least one thread switch priority control bit in a hardware thread switch control register storing thread switch conditions in the multithreaded processor;

a plurality of priority state bits in a thread state register in the multithreaded processor, each of the plurality of priority state bits corresponding to each of the plurality of threads in the multithreaded processor wherein the priority switch instruction can change any of the plurality of priority state bits depending upon the at least one thread switch priority control bit in the thread switch control register.

13. The thread switch manager of claim 12,

wherein the priority switch instruction changes one of the plurality of priority state bits and in response thereto at least one of the plurality of threads of instructions in the multithreaded processor changes priority.

14. The thread switch manager of claim 13, wherein the multithreaded processor switches processing from the active thread in response to the change of priority of the at least one thread of instructions if the at least one thread switch priority control bit is enabled.

15. The thread switch manager of claim 13, wherein the plurality of priority state bits further comprises a plurality of sets, each one of the sets corresponding to a respective one of the plurality of threads of instructions.

16. The thread switch manager of claim 12, wherein said first register and said second register are unitary.

17. The thread switch manager of claim 12, wherein the priority switch instruction does not change any of a plurality of architected registers of the multithreaded processor.

18. The thread switch manager of claim 12, wherein the priority switch instruction can execute on the multithreaded processor without illegal instruction interrupts.

19. The thread switch manager of claim 18, wherein the switch instruction is a no-op instruction.

20. A computer processor, comprising:

(a) means for processing a plurality of threads of instructions in a hardware multithreaded processor;

(b) means for storing a priority state of each of the plurality of threads in a first register;

(c) means for storing a plurality of thread switch conditions in a hardware thread switch control register in the multithreaded processor to cause the multithreaded processor to switch processing from one to another of the plurality of threads;

(d) means for changing the priority state of one of the plurality of threads based on a thread switch event experienced by said one of the plurality of threads or by a thread switch instruction;

(e) means for altering the applicability of at least one thread switch condition to said plurality of threads;

(f) means, responsive to the changing means and the altering means, for determining whether the processing means will switch processing from a first thread to a second thread of the plurality of threads.

21. The computer processor of claim 20 wherein said means for changing the priority state further comprises a signal from an interrupt request.

22. The computer processor of claim 20 wherein said means for changing the priority state comprises at least one software instruction to manipulate priority bits in at least one hardware register.

23. A computer data processing system, comprising:

a hardware multithreaded processor capable of processing at least one thread of instructions and of switching between at least two threads of instructions;

the hardware multithreaded processor comprising a hardware thread switch control register to store thread switch conditions whereupon a thread switch event corresponding to a thread switch condition will result in the multithreaded processor switching between the at least two threads;

a plurality of internal memory units;

a system bus interconnecting the internal memory units to each other and to the multithreaded processor;

a plurality of external connections connecting the multithreaded processor to one or more of the following external devices;

a memory device, a communication device, a computer network, and an input/output device;

a bus interface connecting the external connections to the multithreaded processor; and

a thread switch manager operably connected to the multithreaded processor to change priority of at least one thread of instruction based on a thread switch event experienced by said at least one thread of instruction and/or by a thread switch instruction interacting with a thread switch priority bit in a register thereby changing the applicability of the thread switch conditions to the at least two threads of instructions.