Coded modulation for digital storage in analog memory devices

• US 6,212,654 B1
• Filed: 07/22/1997
• Issued: 04/03/2001
• Est. Priority Date: 07/22/1997
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Lou, Hui-Ling, Sundberg, Carl-Erik Wilhelm
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): Ton, David
• Application Number:
  US08/898,441
• Time in Patent Office: 1,351 Days
• Field of Search: 235/454, 341/98, 341/95, 250/227.23, 375/254, 375/296, 375/295, 365/149, 365/45, 714/773, 714/701, 714/746
• US Class Current: 714/701
• CPC Class Codes: G11C 27/00 Electric analogue stores, e.g. for storing instantaneous values
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: H03M 13/05 using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits H03M13/2906 takes precedence
• CPC Class Codes: H03M 13/23 using convolutional codes, e.g. unit memory codes
• CPC Class Codes: H03M 13/25 Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] modulation codes H03M13/31
• CPC Class Codes: H03M 13/41 using the Viterbi algorithm or Viterbi processors
• CPC Class Codes: H03M 13/413 tail biting Viterbi decoding
• CPC Class Codes: H03M 13/6505 Memory efficient implementations

Abstract

Digital data is stored in an analog memory device using coded modulation techniques. The memory device includes a number of memory cells, each capable of storing one of a number of different levels. A given set of b information bits to be stored in the memory device is first coded in a convolutional or block coder to generate a set of coded bits which includes more than b bits. The set of coded bits is then mapped to one or more corresponding levels, and the one or more levels are each stored in a separate cell of the memory device. In a one-dimensional embodiment, the coding may involve applying a rate 1/2 convolutional code to i least significant bits, i=1, 2, . . . , and mapping the resulting b+i coded bits to one of 2^b+i distinct levels in a one-dimensional AM signal set. In embodiments of the invention which utilize multidimensional signal sets, a given set of bits is mapped to a signal in an m-dimensional signal set, with or without coding of the bits, and each of the m dimensions of the selected signal is then stored as a level in a separate cell of the analog memory device. The invention increases the storage capacity of the memory device for a given readout error probability, or alternatively improves the error probability for a given storage capacity. Readout performance may be further improved by using a multiple read-and-sum unit to generate a readout value for a given stored level based on a sum or average of several different readouts of the stored level.

Claims

1. A method of storing information bits in an analog memory device, the device including a plurality of analog memory cells, the method comprising the steps of:

coding at least a portion of a given set of b of the information bits to generate a corresponding set of coded bits including more than b bits, such that the portion of the information bits subject to the coding is transformed into corresponding coded bits in the set of coded bits;

mapping the set of coded bits to one or more corresponding levels; and

storing each of the one or more levels in one of the analog memory cells;

wherein the mapping step is configured to provide at least one of;

(i) an increase in an effective storage capacity of at least a subset of the analog memory cells; and

(ii) a decrease in a readout error probability of at least a subset of the analog memory cells;

relative to an effective storage capacity and a readout error probability associated with storage of unmapped analog levels in the analog memory cells.

2. The method of claim 1 wherein the coding step includes applying a rate 1/2 convolutional code to i least significant bits, i=1, 2, . . . , of the set of b bits such that the corresponding set of coded bits includes b+i bits.

3. The method of claim 2 wherein the mapping step includes mapping the set of b+i coded bits to one of 2^b+i distinct amplitude levels.

4. The method of claim 1 wherein the mapping step includes mapping the set of coded bits to one of a plurality of signal amplitude levels, wherein each of the plurality of signal amplitude levels corresponds to a signal in a one-dimensional signal set.

5. The method of claim 1 wherein the mapping step includes mapping the set of coded bits to a signal in an m-dimensional signal set, such that each of m levels are used to represent a corresponding one of the dimensions of the signal.

6. The method of claim 5 wherein the storing step includes storing each of the m levels in a separate one of the analog memory cells.

7. The method of claim 1 further including the step of interleaving mapped levels for different sets of coded bits prior to storing the levels in corresponding cells of the memory device.

8. The method of claim 1 wherein the coding and mapping steps further include coding and mapping a first set of b bits using a first type of coded modulation, and coding and mapping a second set of b bits using a second type of coded modulation different than the first type of coded modulation.

9. The method of claim 1 further including the step of generating a single readout value using results of multiple readouts of the level stored in a given one of the analog memory cells.

10. The method of claim 1 further including the step of converting a readout of the stored levels from the memory cells to corresponding sets of bits using a Viterbi decoder.

11. The method of claim 10 wherein the information bits are divided into frames, and the method includes the step of starting a decoding process in the Viterbi decoder at a prior frame in order to provide a reliable estimate of encoder state for decoding a subsequent frame.

12. An analog memory device for storing a plurality of information bits, comprising:

a plurality of analog memory cells;

a coder having an input connected to receive the information bits, the coder coding at least a portion of a given set of b of the information bits to generate a corresponding set of coded bits including more than b bits, such that the portion of the information bits subject to the coding is transformed into corresponding coded bits in the set of coded bits; and

a mapper having an input coupled to an output of the coder and receiving the set of coded bits, wherein the mapper is operative to map the set of coded bits to one or more corresponding levels, such that each of the one or more levels can be stored in one of the plurality of analog memory cells;

wherein the mapper is configured to provide at least one of;

(i) an increase in an effective storage capacity of at least a subset of the analog memory cells; and

(ii) a decrease in a readout error probability of at least a subset of the analog memory cells;

relative to an effective storage capacity and a readout error probability associated with storage of unmapped analog levels in the analog memory cells.

13. The memory device of claim 12 wherein the coder is operative to apply a rate 1/2 convolutional code to i least significant bits of the set of b bits such that the corresponding set of coded bits includes b+i bits.

14. The memory device of claim 13 wherein the mapper is operative to map the set of b+i coded bits to one of 2^b+i distinct amplitude levels.

15. The memory device of claim 12 wherein the mapper is operative to map the set of coded bits to one of a plurality of signal amplitude levels, wherein each of the plurality of signal amplitude levels corresponds to a signal in a one-dimensional signal set.

16. The memory device of claim 12 wherein the mapper is operative to map the set of coded bits to a signal in an m-dimensional signal set, such that each of m levels are used to represent a corresponding one of the dimensions of the signal.

17. The memory device of claim 16 wherein each of the m levels are stored in a separate one of the analog memory cells.

18. The memory device of claim 12 further including an interleaver having an input connected to receive the mapped levels for different sets of coded bits from the mapper, wherein the interleaver is operative to interleave the mapped levels before the levels are stored in the cells.

19. The memory device of claim 12 wherein the coder and mapper are configured so as to provide coding and mapping of a first set of b bits using a first type of coded modulation, and coding and mapping of a second set of b bits using a second type of coded modulation different than the first type of coded modulation.

20. The memory device of claim 12 further including a readout unit having an input coupled to an output of at least one of the memory cells, wherein the readout unit is operative to generate a single readout value using results of multiple readouts of a stored level from a given one of the analog memory cells.

21. The memory device of claim 12 further including a Viterbi decoder for converting a readout of the stored levels from the memory cells to corresponding sets of bits.

22. The memory device of claim 21 wherein the information bits are divided into frames, and a reliable estimate of encoder state for a given frame is obtained by starting a decoding process in the Viterbi decoder at a prior frame.

23. A method of storing information bits in an analog memory device, the device including a plurality of analog memory cells, the method comprising the steps of:

mapping a given set of the information bits to a particular signal in an m-dimensional signal set, the signal including m dimensions; and

storing each of the m dimensions of the signal as a level in a separate one of the analog memory cells.

24. The method of claim 23 wherein the mapping step is part of a coded modulation technique for converting a sequence of symbols, each symbol corresponding to a set of information bits, to a sequence of signals from the m-dimensional signal set in accordance with predetermined conversion rules.

25. The method of claim 24 wherein the coded modulation technique maps a sequence of b-bit symbols to a sequence of signals in the m-dimensional signal set, by (i) encoding the first {tilde over (b)} bits of a set of b parallel bits of a given symbol at a rate of {tilde over (b)}/({tilde over (b)}+1) to generate a total of b+1 bits, (ii) using {tilde over (b)}+1 bits from the encoder to select a particular subset of signals in the m-dimensional signal set, and (iii) using the remainder of the b+1 bits to select a particular signal from the selected subset.

26. The method of claim 23 further including the step of interleaving mapped levels for different sets of bits prior to storing the levels in corresponding cells of the memory device.

27. The method of claim 23 wherein the mapping step further includes mapping a first set of bits using a first type of coded modulation, and mapping a second set of bits using a second type of coded modulation different than the first type of coded modulation.

28. The method of claim 23 further including the step of generating a single readout value using results of multiple readouts of the level stored in a given one of the analog memory cells.

29. An analog memory device for storing a plurality of information bits, comprising:

a plurality of analog memory cells; and

a mapper operative to map a given set of the information bits to a particular signal in an m-dimensional signal set, the signal including m-dimensions, wherein each of the m dimensions of the signal is stored as a level in a separate one of the analog memory cells.

30. The memory device of claim 29 wherein the mapper is part of a coded modulation device which implements a coded modulation technique for converting a sequence of symbols, each symbol corresponding to a set of information bits, to a sequence of signals from the m-dimensional signal set in accordance with predetermined conversion rules.

31. The memory device of claim 30 wherein the coded modulation device maps a sequence of b-bit symbols to a sequence of signals in the m-dimenisional signal set, by (i) encoding the first {tilde over (b)} bits of a set of b parallel bits of a given symbol at a rate of {tilde over (b)}/({tilde over (b)}+1) to generate a total of b+1 bits, (ii) using {tilde over (b)}+1 bits from the encoder to select a particular subset of signals in the m-dimensional signal set, and (iii) using the remainder of the b+1 bits to select a particular signal from the selected subset.

32. The memory device of claim 29 further including an interleaver having an input connected to receive the mapped levels for different sets of coded bits from the mapper, wherein the interleaver is operative to interleave the mapped levels before the levels are stored in the cells.

33. The memory device of claim 29 wherein the mapper is configured so as to provide mapping of a first set of bits using a first type of coded modulation, and mapping of a second set of bits using a second type of coded modulation different than the first type of coded modulation.

34. The memory device of claim 29 further including a readout unit having an input coupled to an output of at least one of the memory cells, wherein the readout unit is operative to generate a single readout value using results of multiple readouts of a stored level from a given one of the analog memory cells.

35. A method of storing information bits in an analog memory device, the device including a plurality of analog memory cells, the method comprising the steps of:

processing a sequence of symbols, each of the symbols corresponding to a set of the information bits, to generate a sequence of signals selected from an m-dimensional signal set, such that each of the signals includes in dimensions; and

storing each of the m dimensions of a given signal in the sequence of signals as a level in a separate one of the analog memory cells.

36. The method of claim 35 wherein the processing step maps a sequence of b-bit symbols to a sequence of signals in the m-dimensional signal set, by (i) encoding the first {tilde over (b)} bits of a set of b parallel bits of a given symbol at a rate of {tilde over (b)}/({tilde over (b)}+1) to generate a total of b+1 bits, (ii) using {tilde over (b)}+1 bits from the encoder to select a particular subset of signals in the m-dimensional signal set, and (iii) using the remainder of the b+1 bits to select a particular signal from the selected subset.

37. An analog memory device for storing a plurality of information bits, comprising:

a plurality of analog memory cells; and

a coded modulation device for processing a sequence of symbols, each of the symbols corresponding to a set of the information bits, to generate a sequence of signals selected from an m-dimensional signal set, such that each of the signals includes m dimensions, and each of the m dimensions of a given signal in the sequence of signals is stored as a level in a separate one of the analog memory cells.

38. The memory device of claim 37 wherein the coded modulation device maps a sequence of b-bit symbols to a sequence of signals in the m-dimensional signal set, by (i) encoding the first {tilde over (b)} bits of a set of b parallel bits of a given symbol at a rate of {tilde over (b)}/({tilde over (b)}+1) to generate a total of b+1 bits, (ii) using {tilde over (b)}+1 bits from the encoder to select a particular subset of signals in the m-dimensional signal set, and (iii) using the remainder of the b+1 bits to select a particular signal from the selected subset.

39. A method of storing information bits in an analog memory device, the device including a plurality of analog memory cells, the method comprising the steps of:

coding at least a portion of a given set of b of the information bits to generate a corresponding set of coded bits including more than b bits, such that the portion of the information bits subject to the coding is transformed into corresponding coded bits in the set of coded bits;

mapping a given set of the coded bits to one or more levels;

storing each of the one or more levels in one of the cells of the analog memory device; and

generating a single readout value using results of multiple readouts of a stored level from a given one of the cells

wherein the mapping step is configured to provide at least one of;

(i) an increase in an effective storage capacity of at least a subset of the analog memory cells; and

(ii) a decrease in a readout error probability of at least a subset of the analog memory cells;

relative to an effective storage capacity and a readout error probability associated with storage of unmapped analog levels in the analog memory cells.

40. The method of claim 39 wherein the generating step includes summing the multiple readouts from the given cell to generate the single readout value.

41. The method of claim 39 wherein the generating step includes averaging the multiple readouts from the given cell to generate the single readout value.

42. An analog memory device for storing a plurality of information bits, comprising:

a plurality of analog memory cells;

a coder operative to code at least a portion of a given set of b of the information bits to generate a corresponding set of coded bits including more than b bits, such that the portion of the information bits subject to the coding is transformed into corresponding coded bits in the set of coded bits;

a mapper operative to map a set of the coded bits to one or more levels, such that each of the one or more levels is stored in one of the plurality of cells; and

a readout unit having an input coupled to an output of a given one of the memory cells, wherein the readout unit is operative to generate a single readout value using results of multiple readouts of a stored level from the given cell;

wherein the mapper is configured to provide at least one of;

(i) an increase in an effective storage capacity of at least a subset of the analog memory cells; and

(ii) a decrease in a readout error probability of at least a subset of the analog memory cells;

relative to an effective storage capacity and a readout error probability associated with storage of unmapped analog levels in the analog memory cells.

43. The memory device of claim 42 wherein the readout unit is operative to sum the multiple readouts from the given cell to generate the single readout value.

44. The memory device of claim 42 wherein the readout unit is operative to average the multiple readouts from the given cell to generate the single readout value.