Graphic representation of circuit analysis for circuit design and timing performance evaluation

• US 6,212,666 B1
• Filed: 11/04/1996
• Issued: 04/03/2001
• Est. Priority Date: 11/04/1996
• Status: Expired due to Term

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Gohl, Karl W., Hissen, Helmut, Donelly, Ross A.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Siek, Vuthe
• Application Number:
  US08/743,488
• Time in Patent Office: 1,611 Days
• Field of Search: 364/488-491, 364/578, 716/2, 716/3, 716/4, 716/5, 716/6
• US Class Current: 716/108
• CPC Class Codes: G06F 30/3312 Timing analysis

Abstract

A method and apparatus that displays a “delay chart” on a display screen, using a variety of user-selected formats and representing delays of a circuit being debugged. These formats include right-to-left and left-to-right displays. The displays can optionally have duplicative paths merged and zero delay paths removed. The invention also allows the designer to select various parts of the delay chart and then automatically highlights related portions of HDL code for the circuit (which also is displayed on the display screen). Conversely, the designer can select portions of the HDL code and the invention will automatically highlight related portions of the delay chart. Thus, the designer can easily determine which parts of the HDL caused large delays in the circuit being designed and can easily change those parts of the HDL in an attempt to obtain more desirable timing.

Claims

1. A method for graphic representation of circuit design and timing analysis, comprising the steps, performed by a data processing system, of:

providing a circuit representation stored in a memory of the data processing system, the circuit representation representing a circuit having at least one path with an associated delay;

generating a Directed Acyclic Graph (DAG) in the memory in accordance with the circuit representation; and

displaying a delay chart on a display device in accordance with the DAG, wherein the delay chart represents the delay of the circuit Path graphically with an edge comprising a graphically distinct portion whose length is proportional to the delay, the delay chart including one or both of a right-to-left delay chart and a left-to-right delay chart, wherein the delay chart facilitates the design and timing analysis of the circuit.

2. The method of claim 1, where the displaying step represents the delay of the circuit as a horizontal line having a length proportional to the delay.

3. The method of claim 1, further including the steps of:

receiving input from a designer indicating that a portion of the delay chart is selected; and

highlighting a portion of a hardware description language (HDL) code displayed on the display device in accordance with the input received by the designer, the highlighted HDL code portion corresponding to the selected portion of the delay chart.

4. The method of claim 3, further including the step, performed before the providing step, of generating the circuit representation in accordance with the HDL code, and

wherein the highlighted HDL code is the HDL code that generated the portion of the DAG corresponding to the selected portion of the delay chart.

5. The method of claim 1, further including the steps of:

receiving input from a designer indicating that a portion of HDL code displayed on a display device is selected; and

highlighting a portion of delay chart in accordance with the input received by the user, where the portion of highlighted delay chart corresponds to the selected portion of the HDL code.

6. The method of claim 5, further including the step, performed before the providing step, of generating the circuit representation in accordance with the HDL code, and

wherein the selected HDL code is the HDL code that generated the portion of the DAG corresponding to the highlighted portion of the delay chart.

7. The method of claim 1, wherein the right-to-left delay chart represents a time to an end point, and wherein the left-to-right delay chart represents another time from a start point.

8. The method of claim 1, wherein the graphically distinct portion is displayed horizontally or vertically with respect to a visual view of a circuit designer.

9. The method of claim 1, wherein the edge graphically couples a first node to a second node and the second node is represented by a graphical element comprising a linear edge aligned with a time period.

10. The method of claim 9, wherein the edge has an end graphically coincident to the linear edge and wherein the graphically distinct portion of the edge is perpendicular to the linear edge.

11. The method of claim 1, wherein the graphically distinct portion of the edge is indicated as separate from a remainder portion of the edge by having the graphically distinct portion have a slope different from a slope of the remainder portion.

12. The method of claim 11, wherein the slope of the graphically distinct portion is set such that it is parallel to a time axis and the slope of the remainder portion is set such that it is at a diagonal to the time axis.

13. The method of claim 1, further comprising:

displaying a right-to-left delay chart along a time axis and relative to an end point, wherein the edge graphically couples a first node to a second node, wherein a second edge, representing a second delay of a second circuit path, graphically couples a third node to the first node and has a graphically distinct portion whose length is proportional to the delay, wherein a first end of the graphically distinct portion of the edge is further from the end point than a second end of the graphically distinct portion of the second edge and wherein a graphical element representing the first node is graphically connected to the first end and is graphically coupled, through another graphically distinct portion of the second edge, to the second end.

14. The method of claim 1, further comprising:

displaying a left-to-right delay chart along a time axis and relative to a start point, wherein the edge graphically couples a first node to a second node, wherein a second edge, representing a second delay of a second circuit path, graphically couples a third node to the first node and has a graphically distinct portion whose length is proportional to the delay, wherein a first end of the graphically distinct portion of the edge is further from the start point than a second end of the graphically distinct portion of the second edge and wherein a graphical element representing the first node is graphically connected to the first end and is graphically coupled, through another graphically distinct portion of the second edge, to the second end.

15. An apparatus for graphic representation of circuit design and timing analysis in a data processing system, comprising:

a first portion configured to provide a circuit representation stored in a memory of the data processing system, the circuit representation representing a circuit having at least one path with an associated delay;

a second portion coupled to the first portion and configured to generate a Directed Acyclic Graph (DAG) in the memory in accordance with the circuit representation; and

a third portion coupled to the second portion and configured to display the graphic representation including in the form of a delay chart in accordance with the DAG, the delay chart representing the delay of the circuit Path graphically with an edge comprising a graphically distinct portion whose length is proportional to the delay, the delay chart including one or both of a right-to-left delay chart and a left-to-right delay chart, wherein the delay chart facilitates the design and timing analysis of the circuit.

16. The apparatus of claim 15, in which the delay of the circuit is represented as a horizontal line having a length proportional to the delay.

17. The apparatus of claim 15, further including:

a fourth portion coupled to the first portion and configured to generate, before the first portion provides, a representation of the circuit in accordance with a hardware description language (HDL) code, the HDL code being used for then generating the DAG.

18. The apparatus of claim 17, further including:

a fifth portion coupled to the third portion and configured to receive input from a designer indicating that a portion of the delay chart is being selected; and

a sixth portion coupled to the fifth portion and configured to highlight in accordance with the input received from the designer a portion of the HDL code being displayed, the highlighted HDL code portion corresponding to the selected portion of the delay chart.

19. The apparatus of claim 17, further including:

a fifth portion coupled to the third portion and configured to receive input from a designer indicating that a portion of the HDL code being displayed is being selected; and

a sixth portion coupled to the fifth portion and configured to highlight in accordance with the input received from the designer a portion of the delay chart being displayed, the highlighted portion corresponding to the selected portion of the HDL code.

20. The apparatus of claim 17, further including:

a fifth portion coupled to the third portion and configured to receive input from a designer indicating that a portion of one of the HDL code and the delay chart being displayed is being selected; and

a sixth portion coupled to the fifth portion and configured to highlight in accordance with the input received from the designer one of a portion of the delay chart which corresponds to the HDL code portion being selected and a portion of the HDL code which corresponds to the delay chart portion being selected.

21. The apparatus of claim 15, in which the right-to-left delay chart represents a time to an end point, and wherein the left-to-right delay chart represents another time from a start point.

22. An apparatus for graphic representation of circuit design and timing analysis in a data processing system, comprising:

means for providing a circuit representation stored in a memory of the data processing system, the circuit representation representing a circuit having at least one path with an associated delay;

means coupled to the providing means for generating a [Direct] Directed Acyclic Graph (DAG) in the memory in accordance with the circuit representation; and

means coupled to the generating means for displaying the graphic representation including in the form of a delay chart in accordance with the DAG, the delay chart representing the delay of the circuit path graphically with an edge comprising a graphically distinct portion whose length is proportional to the delay, the delay chart including one or both of a right-to-left delay chart and a left-to-right delay chart, wherein the delay chart facilitates the design and timing analysis of the circuit.

23. The apparatus of claim 22, in which the delay of the circuit is represented as a horizontal line having a length proportional to the delay.

24. The apparatus of claim 22, further including:

means coupled to the providing means for generating, before providing, a representation of the circuit in accordance with a hardware description language (HDL) code, the HDL code being used for then generating the DAG.

25. The apparatus of claim 24, further including:

means coupled to the display means for receiving input from a designer indicating that a portion of the delay chart is being selected; and

means coupled to the receiving means for highlighting in accordance with the input received from the designer a portion of the HDL code being displayed, the highlighted HDL code portion corresponding to the selected portion of the delay chart.

26. The apparatus of claim 24, further including:

means coupled to the display means for receiving input from a designer indicating that a portion of the HDL code being displayed is being selected; and

means coupled to the receiving means for highlighting in accordance with the input received from the designer a portion of the delay chart being displayed, the highlighted portion corresponding to the selected portion of the HDL code.

27. The apparatus of claim 24, further including:

means coupled to the display means for receiving input from a designer indicating that a portion of one of the HDL code and the delay chart which is being displayed is being selected; and

means coupled to the receiving means for highlighting in accordance with the input received from the designer one of a portion of the delay chart which corresponds to the HDL code portion being selected and a portion of the HDL code which corresponds to the delay chart portion being selected.

28. The apparatus of claim 22, in which the right-to-left delay chart represents a time to an end point, and wherein the left-to-right delay chart represents another time from a start point.

29. A computer readable medium including instructions for graphic representation of circuit design and timing analysis in a data processing system, the instructions for:

providing a circuit representation stored in a memory of the data processing system, the circuit representation representing a circuit having at least one path with an associated delay;

generating a Directed Acyclic Graph (DAG) in the memory in accordance with the circuit representation; and

displaying the graphic representation including in the form of a delay chart in accordance with the DAG, the delay chart representing the delay of the circuit path graphically with an edge comprising a graphically distinct portion whose length is proportional to the delay, the delay chart including one or both of a right-to-left delay chart and a left-to-right delay chart, wherein the delay chart facilitates the design and timing analysis of the circuit.

30. The computer readable medium of claim 29, wherein the delay of the circuit is represented as a horizontal line having a length proportional to the delay.

31. The computer readable medium of claim 29, further including instructions for:

generating, before providing, a representation of the circuit in accordance with a hardware description language (HDL) code, the HDL code being used for then generating the DAG.

32. The computer readable medium of claim 31, further including instructions for:

receiving input from a designer indicating that a portion of the delay chart is being selected; and

highlighting in accordance with the input received from the designer a portion of the HDL code being displayed, the highlighted HDL code portion corresponding to the selected portion of the delay chart.

33. The computer readable medium of claim 31, further including instructions for:

receiving input from a designer indicating that a portion of the HDL code being displayed is being selected; and

highlighting in accordance with the input received from the designer a portion of the delay chart being displayed, the highlighted portion corresponding to the selected portion of the HDL code.

34. The computer readable medium of claim 31, further including instructions for:

receiving input from a designer indicating that a portion of one of the HDL code and the delay chart which is being displayed is being selected; and

highlighting in accordance with the input received from the designer one of a portion of the delay chart which corresponds to the HDL code portion being selected and a portion of the HDL code which corresponds to the delay chart portion being selected.

35. The computer readable medium of claim 29, wherein the right-to-left delay chart represents a time to an end point, and wherein the left-to-right delay chart represents another time from a start point.