Integrated circuit test coverage evaluation and adjustment mechanism and method

• US 6,212,667 B1
• Filed: 07/30/1998
• Issued: 04/03/2001
• Est. Priority Date: 07/30/1998
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Geer, Charles Porter, Meyer, Jerome Martin, Ur, Shmuel, Kalla, Ronald Nick
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Speight, Jibreel
• Application Number:
  US09/126,142
• Time in Patent Office: 978 Days
• Field of Search: 703/14, 716/6, 716/5, 714/6, 714/35, 714/739, 714/724, 714/738, 714/38, 714/741
• US Class Current: 716/136
• CPC Class Codes: G01R 31/31835 Analysis of test coverage or failure detectability

Abstract

Testcases are run to test the design of an integrated circuit. The coverage of the testcases is evaluated and compared against one or more microarchitecture models that define the behavior of a portion of the integrated circuit. If the coverage of the testcases is not adequate, new testcases are generated to test the previously untested behavior specified in the microarchitecture models.

Claims

1. An apparatus comprising:

at least one processor;

a memory coupled to the at least one processor;

an integrated circuit design residing in the memory;

a plurality of testcases residing in the memory for testing the integrated circuit design; and

a test coverage evaluation and adjustment mechanism residing in the memory and executed by the at least one processor, the test coverage evaluation and adjustment mechanism evaluating test coverage for the plurality of testcases, the test coverage comprising a measure of how completely the plurality of testcases tests the integrated circuit design, the test coverage evaluation and adjustment mechanism causing new testcases to be automatically generated that are biased to more thoroughly test the integrated circuit design if the test coverage is inadequate.

2. The apparatus of claim 1 wherein the test coverage is inadequate if the test coverage is below a predetermined value.

3. The apparatus of claim 1 further comprising at least one microarchitecture model residing in the memory, the at least one microarchitecture model defining behavior for at least a portion of the integrated circuit design.

4. The apparatus of claim 1 wherein the integrated circuit design comprises a design of a super scaler microprocessor having a plurality of instruction pipelines, the apparatus further comprising an interdependency microarchitecture model residing in the memory, the interdependency microarchitecture model defining a plurality of interdependencies between the plurality of instruction pipelines.

5. The apparatus of claim 1 further comprising a testcase definition file residing in the memory, wherein the test coverage evaluation and adjustment mechanism causes new testcases to be automatically generated that are biased to more thoroughly test the integrated circuit design by modifying the testcase definition file.

6. An apparatus comprising:

at least one processor;

a memory coupled to the at least one processor;

an integrated circuit design residing in the memory;

a plurality of testcases residing in the memory for testing the integrated circuit design; and

means for automatically generating at least one new testcase to test the integrated circuit design based on comparing

     1) the results of applying the plurality of testcases to the integrated circuit design with

     2) at least one microarchitecture model of the integrated circuit design.

7. The apparatus of claim 6 wherein the at least one microarchitecture model defines behavior for at least a portion of the integrated circuit design.

8. The apparatus of claim 6 wherein the integrated circuit design comprises a design of a super scaler microprocessor having a plurality of instruction pipelines, the apparatus further comprising an interdependency microarchitecture model residing in the memory, the interdependency microarchitecture model defining a plurality of interdependencies between the plurality of instruction pipelines.

9. A method for testing an integrated circuit design, the method comprising the step of:

automatically generating at least one new testcase to test the integrated circuit design based on comparing

     1) the results of applying a plurality of testcases to the integrated circuit design with

     2) at least one microarchitecture model of the integrated circuit design.

10. The method of claim 9 wherein the at least one microarchitecture model defines behavior for at least a portion of the integrated circuit design.

11. The method of claim 9 wherein the integrated circuit design comprises a design of a super scaler microprocessor having a plurality of instruction pipelines, and wherein the at least one microarchitecture model comprises an interdependency microarchitecture model that defines a plurality of interdependencies between the plurality of instruction pipelines.

12. The method of claim 9 wherein the step of automatically generating at least one new testcase comprises the steps of:

modifying a testcase definition file that provides parameters for biasing the generation of the at least one new testcase; and

a testcase generator automatically generating the at least one new testcase in accordance with the modified testcase definition file.

13. A method for testing an integrated circuit design, the method comprising the steps of:

(A) applying a plurality of testcases to a simulation model of the integrated circuit design;

(B) providing at least one microarchitecture model of the integrated circuit design, the microarchitecture model defining behavior for at least a portion of the integrated circuit design;

(C) comparing the results of applying the plurality of testcases to the simulation model of the integrated circuit design to the at least one microarchitecture model; and

(D) automatically generating at least one new testcase that provides improved test coverage based on the compared results.

14. The method of claim 13 wherein the integrated circuit design comprises a design of a super scaler microprocessor having a plurality of instruction pipelines, and wherein the at least one microarchitecture model comprises an interdependency microarchitecture model that defines a plurality of interdependencies between the plurality of instruction pipelines.

15. The method of claim 13 wherein the step of automatically generating at least one new testcase comprises the steps of:

modifying a testcase definition file that provides parameters for biasing the generation of the at least one new testcase; and

a testcase generator automatically generating the at least one new testcase in accordance with the modified testcase definition file.

16. The method of claim 13 further comprising the steps of:

(E) applying the at least one new testcase to the simulation model; and

(F) repeating steps (C), (D) and (E) until a predetermined level of test coverage is achieved.

17. A product comprising a regression suite of all the testcases generated by the method of claim 16.

18. A computer readable program product comprising:

(A) a test coverage evaluation and adjustment mechanism that evaluates test coverage for a plurality of testcases for an integrated circuit design, the test coverage comprising a measure of how completely the plurality of testcases tests the integrated circuit design, the test coverage evaluation and adjustment mechanism causing new testcases to be automatically generated that are biased to more thoroughly test the integrated circuit design if the test coverage is inadequate; and

(B) computer readable signal bearing media bearing the test coverage evaluation and adjustment mechanism.

19. The program product of claim 18 wherein the signal bearing media comprises recordable media.

20. The program product of claim 18 wherein the signal bearing media comprises transmission media.

21. The program product of claim 18 wherein the test coverage is inadequate if the test coverage is below a predetermined value.

22. The program product of claim 18 further comprising at least one microarchitecture model residing in the memory, the at least one microarchitecture model defining behavior for at least a portion of the integrated circuit design.

23. The program product of claim 18 wherein the integrated circuit design comprises a design of a super scaler microprocessor having a plurality of instruction pipelines, the apparatus further comprising an interdependency microarchitecture model residing in the memory, the interdependency microarchitecture model defining a plurality of interdependencies between the plurality of instruction pipelines.

24. The program product of claim 18 further comprising a testcase definition file wherein the test coverage evaluation and adjustment mechanism causes new testcases to be automatically generated that are biased to more thoroughly test the integrated circuit design by modifying the testcase definition file.

25. An apparatus comprising:

at least one processor;

a memory coupled to the at least one processor;

an integrated circuit design residing in the memory;

a testcase generator that automatically generates a first plurality of testcases for testing the integrated circuit design according to information in a testcase definition file;

a gate level cycle simulator residing in the memory that applies the first plurality of testcases to the integrated circuit design residing in the memory;

a test coverage evaluation and adjustment mechanism residing in the memory and executed by the at least one processor, the test coverage evaluation and adjustment mechanism evaluating test coverage for the first plurality of testcases as applied by the gate level cycle simulator, the test coverage comprising a measure of how completely the first plurality of testcases tests the integrated circuit design, the test coverage evaluation and adjustment mechanism modifying the testcase definition file if the test coverage is inadequate to cause the testcase generator to automatically generate a second plurality of testcases that are biased to more thoroughly test the integrated circuit design, thereby causing the gate level cycle simulator to iteratively apply testcases to the integrated circuit design.

26. A method for testing an integrated circuit design residing in a memory, the method comprising the step of:

(1) generating a first plurality of testcases for testing the integrated circuit design according to information in a testcase definition file;

(2) applying the first plurality of testcases to the integrated circuit design;

(3) evaluating test coverage of the testcases as applied to the integrated circuit design;

(4) if the test coverage is inadequate, performing the steps of;

(4A) modifying the testcase definition file;

(4B) automatically generating a new plurality of testcases; and

(4C) repeating steps (3) and (4) until the test coverage is adequate.