Method of fabricating a multi-chip module
First Claim
1. A method of manufacturing a multi-chip module, comprising:
- providing a carrier substrate having a top side and a bottom side, a plurality of openings therethrough, at least one recess partially extending into said carrier substrate from said bottom side and aligned with one of said plurality of openings, and a plurality of conductive traces on said top side proximate each of said plurality of openings;
attaching a plurality of semiconductor dice each having an active surface with a plurality of bond pads disposed thereover adjacent said bottom side of said carrier substrate such that a portion of an active surface of each of said plurality of semiconductor dice is aligned with one of said plurality of openings and said plurality of bond pads is exposed therethrough, at least one of said plurality of semiconductor dice being secured at least partially within said at least one recess; and
electrically connecting at least one of said plurality of conductive traces to at least one of said plurality of bond pads of each of said plurality of semiconductor dice through an intermediate conductive element to form a circuit including said conductive traces.
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Accused Products
Abstract
A lead-over-chip single-in-line memory module (LOC SIMM) and method of manufacturing is disclosed that provides for shortened wire bonds and ease of rework for unacceptable semiconductor dice. More specifically, the LOC SIMM of the present invention includes a plurality of slots extending through a circuit board with an equal number of semiconductor dice attached thereto such that the active surfaces of the dice are exposed through the slots. Wire bonds or TAB connections are made from the exposed active surface of the die, through the slot, and to contacts on the top surface of the circuit board. Dice proven unacceptable during burn-in and electrical testing of the module are replaced by known good dice (KGD) by breaking their respective wire bonds, attaching a KGD to the circuit board, and forming new electrical connections between the KGD and the circuit board.
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Citations
16 Claims
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1. A method of manufacturing a multi-chip module, comprising:
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providing a carrier substrate having a top side and a bottom side, a plurality of openings therethrough, at least one recess partially extending into said carrier substrate from said bottom side and aligned with one of said plurality of openings, and a plurality of conductive traces on said top side proximate each of said plurality of openings;
attaching a plurality of semiconductor dice each having an active surface with a plurality of bond pads disposed thereover adjacent said bottom side of said carrier substrate such that a portion of an active surface of each of said plurality of semiconductor dice is aligned with one of said plurality of openings and said plurality of bond pads is exposed therethrough, at least one of said plurality of semiconductor dice being secured at least partially within said at least one recess; and
electrically connecting at least one of said plurality of conductive traces to at least one of said plurality of bond pads of each of said plurality of semiconductor dice through an intermediate conductive element to form a circuit including said conductive traces. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method of fabricating a multi-chip module, comprising:
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providing a carrier substrate having a top side and a bottom side and a plurality of openings extending therethrough, a plurality of semiconductor dice each having an active surface including a plurality of bond pads thereon attached to said carrier substrate on said bottom side with said plurality of bond pads of each of said semiconductor dice exposed through an opening, at least some of said bond pads being electrically connected via intermediate conductive elements to conductors carried on said top side and proximate an opening through which said connected plurality of bond pads are exposed;
testing said semiconductor dice after attachment and connection to said carrier substrate and establishing the presence of at least one bad die on said carrier substrate; and
attaching at least another die to said carrier substrate and electrically connecting said at least another die to said conductors in place of said at least one bad die without detaching said at least one bad die from said carrier substrate. - View Dependent Claims (16)
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Specification