Capacitor for integrated circuit and its fabrication method

• US 6,214,660 B1
• Filed: 10/23/1998
• Issued: 04/10/2001
• Est. Priority Date: 12/28/1994
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electronics Corp (Panasonic Holdings Corporation)
• Inventors: Fujii, Eigi, Uemoto, Yasuhiro, Arita, Koji, Shimada, Yasuhiro, Inoue, Atsuo, Nagano, Yoshihisa, Azuma, Masamichi, Izutsu, Yasufumi
• Primary Examiner(s): WILCZEWSKI, MARY A
• Assistant Examiner(s): Lin, Yung A.
• Application Number:
  US09/177,620
• Time in Patent Office: 900 Days
• Field of Search: 438/240, 438/608, 438/627, 438/628, 438/643, 438/644, 438/650, 438/653, 438/393
• US Class Current: 438/240
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 28/56 the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers
• CPC Class Codes: H10B 53/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors

Abstract

A method for fabricating a capacitor for an integrated circuit, comprising the steps of forming a titanium film for an adhesion layer over a substrate, forming a titanium dioxide film for a diffusion barrier layer by annealing the titanium film after ion-implantation of oxygen ion into a surface region of the titanium film so as to change titanium in the surface region to titanium dioxide, and forming a high dielectric constant capacitor on the titanium dioxide film.

Claims

1. A method for fabricating a capacitor for an integrated circuit comprising the steps of:

forming an adhesion layer of a metal over a substrate;

implanting non-metal ions into a surface region of said adhesion layer;

forming a diffusion barrier layer of a compound of said metal and non-metal such that said diffusion barrier layer is positioned on said adhesion layer by annealing said adhesion layer after said ion implantation of said non-metal into said surface region of said adhesion layer so as to change said metal in said surface region to said compound;

forming a bottom electrode layer of a noble metal on said diffusion barrier layer;

forming a dielectric layer of a metal oxide on said bottom electrode layer;

forming a top electrode layer of a conductive metal on said dielectric layer;

etching said top electrode layer and dielectric layer selectively;

etching said bottom electrode layer selectively; and

etching said diffusion barrier layer and adhesion layer selectively.

2. A method for fabricating a capacitor for an integrated circuit, said method comprising the steps of:

forming an adhesion layer comprising metal over a substrate;

forming a diffusion barrier layer such that said diffusion barrier layer is positioned on said adhesion layer by annealing said adhesion layer in a reactive ambient so as to change said metal to a compound of metal and non-metal;

forming a bottom electrode layer of a noble metal on said diffusion barrier layer;

forming a dielectric layer of a metal oxide on said bottom electrode layer;

forming a top electrode layer of a conductive metal on said dielectric layer;

etching said top electrode layer and said dielectric layer selectively;

etching said bottom electrode layer selectively; and

etching said diffusion barrier layer and said adhesion layer selectively.

3. The method of claim 2,

wherein said adhesion layer is titanium, said reactive ambient is oxygen and said diffusion barrier layer is titanium oxide.