Semiconductor memory device having memory cells each having a conductive body of booster plate and a method for manufacturing the same

• US 6,214,665 B1
• Filed: 11/05/1998
• Issued: 04/10/2001
• Est. Priority Date: 11/07/1997
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Sakui, Koji
• Primary Examiner(s): BOOTH, RICHARD A
• Application Number:
  US09/186,182
• Time in Patent Office: 887 Days
• Field of Search: 438/257-267
• US Class Current: 438/257
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A booster plate is insulatively formed on a silicon semiconductor substrate with a first gate insulating film disposed therebetween. A floating gate which forms a capacitor in cooperation with part of at least the upper surface of the booster plate is insulatively formed on the booster plate with a second insulating film disposed therebetween. Further, a control gate is insulatively formed on the floating gate with a third insulating film disposed therebetween.

Claims

1. A method for manufacturing a semiconductor memory device having memory cells, comprising the steps of:

forming a first insulating film on a semiconductor substrate;

forming plate electrodes on the first insulating film, which are patterned along a wiring direction of control gates of the memory cells;

forming second insulating films on the plate electrodes;

forming third insulating films on the semiconductor substrate such that the third insulating films are located between adjacent ones of the plate electrodes;

forming floating gates insulatively on part of upper surfaces and side surfaces of the plate electrodes with the second insulating films disposed therebetween and on the third insulating film;

forming fourth insulating films on the floating gates; and

forming control gates on the fourth insulating films.

2. A method according to claim 1, wherein said memory cells constitute at least one memory cell unit and which further comprises a step of implanting ions into a region that functions as a source and drain of said at least one memory cell unit, thereby forming a self-aligned diffusion layer by using said plate electrodes and said control gates.

3. A method according to claim 2, wherein said memory cell unit has a NAND structure.

4. A method for manufacturing a semiconductor memory device having at least one memory cell unit including a plurality of memory cells, comprising the steps of:

forming a first insulating firm on a semiconductor substrate;

forming a first conductive film on the first insulating film;

patterning the first conductive film into a preset pattern and forming element isolation trenches in the semiconductor substrate with the preset pattern used as a mask;

filling an insulating material into the element isolation trenches to form element isolation regions;

forming a second conductive film on the semiconductor substrate;

patterning the second and first conductive films into a plurality of linear portions along the wiring direction of control gates of the memory cells;

forming a second insulating film on laminated bodies of the second and first conductive films patterned into the linear portions;

forming a third conductive film on the second insulating film;

forming isolation trenches in the third conductive film above the element isolation regions which are adjacent in the control gate line direction of the memory cells;

forming a third insulating film on the third conductive film;

forming a fourth conductive film on the third insulating film;

patterning the fourth conductive film, third insulating film and third conductive film in a self-alignment manner to form control gate lines formed of the fourth conductive film and floating gates formed of the third conductive film at least between the laminated bodies of the second and first conductive films; and

forming diffusion layers in a self-alignment manner in regions acting as source/drain regions of the at least one memory cell unit by ion-implantation by use of the laminated bodies of the second and first conductive films patterned into the linear portions and the control gate lines.