Method to increase wafer utility by implementing deep trench in scribe line

• US 6,214,703 B1
• Filed: 04/15/1999
• Issued: 04/10/2001
• Est. Priority Date: 04/15/1999
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Chen-Yu, Chen, Horng-Wen
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Zarneke, David A.
• Application Number:
  US09/292,363
• Time in Patent Office: 726 Days
• Field of Search: 438/462, 438/464, 438/734, 438/976
• US Class Current: 438/462
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: Y10S 438/976 Temporary protective layer

Abstract

A method that teaches the formation of deep trenches within the surface of a semiconductor wafer, these deep trenches are used to separate the wafer into individual chips by applying stress to the wafer. The formation of the deep trenches uses exposing a thick layer of photoresist followed by etching. The etching is a two step etch, a stabilization etch and a main etch. The stress used to separate the wafer into individual chips can be invoked by applying physical force to the wafer.

Claims

1. A method of making a plurality of individual integrated circuit chips from a semiconductor wafer, said wafer having a major surface, said method comprising the steps of:

depositing a protective layer on the surface of said wafer;

exposing pre-selected portions of said protective layer forming windows which expose said wafer in the regions to be scribed, wherein said exposing creates a pattern of scribe lines over the surface of said wafer, said scribe lines having line width in the x and the y direction of between 7.5 and 12.5 um, whereby said pre-selected portions are aligned with an alignment mark pattern;

etching said exposed pre-selected portions of the surface of said wafer;

removing said protective layer; and

stressing said wafer until said wafer breaks along said pre-selected areas.

2. The method of claim 1 wherein said depositing a protective layer is depositing a photo resist coating to a thickness of between 3.5 and 7.9 um. on the surface of said semiconductor wafer.

3. The method of claim 1 wherein said etching is applying a two step etching process whereby the first etch is a stabilization etch and the second etch is the main etch.

4. The method of claim 3 wherein said first etch is an etch that stabilizes the etching environment in preparation for the main etch that is to follow said first etch having etching parameters of between 700 and 800 milli Torr chamber pressure, 0 Watt RF power applied, with an etchant gas mixture of between 70 and 90 SCCM of CF₄ together with between 11 and 15 SCCM of O₂ together with between 5 and 7 Torr of B—

He said first etch being applied for a time between 25 and 35 seconds.

5. The method of claim 3 wherein said second etch is the main etch said main etch having etching parameters of between 700 and 800 milli Torr chamber pressure, between 240 and 310 Watt RF power applied, with an etchant gas mixture of between 70 and 90 SCCM of CF₄ together with between 11 and 15 SCCM of O₂ together with between 5 and 7 Torr of B—

He said second step being applied for a time between 1000 and 1400 seconds.

6. The method of claim 5 whereby said main etch creates a scribe line pattern whereby the cross section of each scribe line has a width of between 7.5 and 12.5 um. and a depth of between 6.00 and 8.00 um.

7. The method of claim 1 wherein said removing said protective layer is a dry ashing process.

8. The method of claim 1 wherein said stressing said wafer is applying physical force to every corner of said window thereby separating said individual integrated circuits adjacent to said corners.

9. The method of claim 1 wherein said protective layer is formed by oxidation of the surface of said semiconductor wafer.

10. The method of claim 1 further in combination with repeating said method of making a plurality of individual integrated circuit chips said repetition containing the deposition of a protective layer of a thickness between 10 and 100 um. in combination with said first etch and said second etch process followed by the removal of said protective layer said repetition to be performed in sequence to the point where said trench exhibits a depth of between 5 and 100 um said method to be applied to wafers with a thickness in excess of approximately 200 um.

11. A method of making a plurality of individual integrated circuit chips from a semiconductor wafer, said wafer having a major surface, said method comprising the steps of:

depositing a protective layer on the surface of said wafer;

exposing pre-selected portions of said protective layer forming a pattern of scribe lines over the surface of said wafer said scribe lines having a line width in the X and the Y direction of between 7.5 and 12.5 um whereby said pre-selected portions are aligned with an alignment mark pattern;

etching said exposed pre-selected portions whereby said etching consists of a stabilization etch followed by a main etch said stabilization etch having etching parameters of between 700 and 800 milli Torr chamber pressure, 0 Watt RF power applied, with an etchant gas mixture of between 70 and 90 SCCM of CF₄ together with between 11 and 15 SCCM of O₂ together with between 5 and 7 Torr of B—

He said first etch being applied for a time between 25 and 35 seconds whereby said main etch having etching parameters of between 700 and 800 milli Torr chamber pressure, between 240 and 310 Watt RF power applied, with an etchant gas mixture of between 70 and 90 SCCM of CF₄ together with between 11 and 15 SCCM of O₂ together with between 5 and 7 Torr of B—

He said second etch being applied for a time between 1000 and 1400 seconds;

removing said protective layer; and

stressing said wafer until said wafer breaks along said pre-selected areas.

12. The method of claim 11 further in combination with repeating said method of making a plurality of individual integrated circuit chips said repetition containing the deposition of a protective layer of a thickness between 10 and 100 um. in combination with said stabilization etch followed by said main etch followed by the removal of said protective layer said repetition to be performed in sequence to the point where said trench exhibits a depth of between 5 and 100 um said method to be applied to wafers with a thickness in excess of approximately 200 um.

13. The method of claim 11 wherein said stressing said wafer is applying physical force to every corner of said window thereby separating said individual integrated circuits adjacent to said corners.