MOSFET having self-aligned gate and buried shield and method of making same

• US 6,215,152 B1
• Filed: 08/05/1998
• Issued: 04/10/2001
• Est. Priority Date: 08/05/1998
• Status: Expired due to Term

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Hebert, Francois
• Primary Examiner(s): Lee, Eddie C.
• Assistant Examiner(s): Warren, Matthew E.
• Application Number:
  US09/130,192
• Time in Patent Office: 979 Days
• Field of Search: 257/249, 257/329, 257/333, 257/335, 257/340, 257/409, 257/488, 257/487, 257/491, 257/508, 438/159, 438/197, 438/267, 438/299, 438/454
• US Class Current: 257/340
• CPC Class Codes: H01L 21/2815 part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A MOSFET has a buried shield plate under the gate and over the drain with the gate being formed on the periphery of the buried shield plate as a self-aligned structure with minimal or no overlap of the gate over the shield plate. Methods of fabricating the MOSFET are disclosed.

Claims

1. A lateral MOS transistor comprising

a semiconductor substrate having a major surface,

a source region and a drain region formed in the major surface and spaced apart by a channel region,

a shield plate formed on said major surface over a portion of the drain region and adjacent to the channel region, the shield plate extending above the major surface and insulated therefrom by a dielectric, and

a gate positioned over the channel region and abutting a side of the shield plate facing the source region, the gate having minimal or no overlap of the shield plate.

2. The lateral MOS transistor as defined by claim 1 wherein the gate is formed on the periphery of the shield plate by a self-aligned deposition and etch of gate material.

3. The lateral MOS transistor as defined by claim 1 and further including a contact to the shield plate formed on the major surface.

4. The lateral MOS transistor as defined by claim 3 and further including a contact to the gate formed on the major surface.

5. The lateral MOS transistor as defined by claim 1 wherein the substrate includes a P+ substrate and a P−

epitaxial layer, the source and drain regions comprising N+ doped regions in the major surface.

6. The lateral MOS transistor as defined by claim 5 wherein the drain further includes an N−

region extending from the N+ doped drain region to the channel region and under the shield plate.

7. The lateral MOS transistor as defined by claim 6 wherein the transistor comprises a LDMOS transistor.

8. The lateral MOS transistor as defined by claim 7 and further including a shield metal overlying the shield plate and insulated therefrom.

9. The lateral MOS transistor as defined by claim 1 and further including a contact to the shield plate and means for applying a voltage potential to the contact.

10. The lateral MOS transistor as defined by claim 9 wherein the voltage potential is ground.

11. A vertical MOS transistor comprising

a semiconductor substrate of first conductivity type having first and second major opposing surfaces,

a doped region of a second conductivity type formed in the first surface, the doped region surrounding a surface area of the semiconductor substrate of first conductivity type,

a source region of the first conductivity type formed in the doped region and spaced from the surface area of the semiconductor substrate by a channel region within the doped region,

a shield plate overlying the surface area and adjacent to the channel region, the shield plate extending above the surface area and insulated therefrom by dielectric, and

a gate positioned over the channel region and abutting the shield plate, the gate having minimal or no overlap of the shield plate,

whereby the substrate functions as a drain for the transistor.

12. The vertical MOS transistor as defined by claim 11 wherein the gate is formed on the periphery of the shield plate by a self-aligned deposition and etch of gate material.

13. The vertical MOS transistor as defined by claim 11 wherein the substrate comprises an N+ doped substrate and N−

doped epitaxial layer.

14. The vertical MOS transistor as defined by claim 11 and further including a contact to the shield plate and means for applying a voltage potential to the contact.

15. The vertical MOS transistor as defined by claim 14 wherein the voltage potential is ground.