Elevated image sensor array which includes isolation between uniquely shaped image sensors

• US 6,215,164 B1
• Filed: 07/26/1999
• Issued: 04/10/2001
• Est. Priority Date: 07/26/1999
• Status: Expired due to Term

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Agilent Technologies, Inc.
• Inventors: Cao, Min, Ma, Shawming, Ray, Gary W, Theil, Jeremy A, Vook, Dietrich W
• Primary Examiner(s): Lee, Eddie C.
• Assistant Examiner(s): Ortiz, Edgardo
• Application Number:
  US09/361,342
• Time in Patent Office: 624 Days
• Field of Search: 257/431, 257/434, 257/440, 257/444, 257/430
• US Class Current: 257/431
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/14636 Interconnect structures

Abstract

An image pixel sensor array. The image pixel sensor array includes a substrate. An interconnect structure is formed adjacent to the substrate. A plurality of image pixel sensors are formed adjacent to the interconnect structure. Each image pixel sensor includes a pixel electrode, and an I-layer formed adjacent to the pixel electrode. The I-layer includes a first surface adjacent to the pixel electrode, and a second surface opposite the first surface. The first surface includes a first surface area which is less than a second surface area of the second surface. The image pixel sensor array further includes an insulating material between each image pixel sensor, and a transparent electrode formed over the image pixel sensors. The transparent electrode electrically connects the image pixel sensors and the interconnect structure.

Claims

1. An image pixel sensor array comprising:

a substrate comprising electronic circuitry;

an interconnect structure adjacent to the substrate;

a plurality of image pixel sensors formed adjacent to the interconnect structure, each image pixel sensor comprising;

a pixel electrode;

an I-layer, the I-layer comprising a first surface adjacent to the pixel electrode, a second surface opposite the first surface, the first surface having a first surface area which is less than a second surface area of the second surface;

the image pixel sensor array further comprising;

an insulating material between each image pixel sensor; and

a transparent electrode formed over the image pixel sensors, the transparent electrode electrically connected to the image pixel sensors and the interconnect structure.

2. The image pixel sensor array as recited in claim 1, wherein each image pixel sensor further comprises a separate P-layer section formed adjacent to the I-layer.

3. The image pixel sensor array as recited in claim 1, wherein each image pixel sensor further comprises a P-layer, wherein the P-layer extends adjacently to a plurality of separate I-layers.

4. The image pixel sensor array as recited in claim 1, wherein each pixel electrode comprises an N-layer.

5. The image pixel sensor array as recited in claim 1, wherein the interconnect structure electrically interconnects the pixel electrodes to the substrate.

6. The image pixel sensor array as recited in claim 1, wherein the I-layer sections and the pixel electrodes comprise amorphous silicon.

7. The image pixel sensor array as recited in claim 2, wherein each P-layer section comprises amorphous silicon.

8. The image pixel sensor array as recited in claim 3, wherein the P-layer comprises amorphous silicon.

9. The image pixel sensor array as recited in claim 1, wherein the inner surface of the transparent electrode is electrically connected to the interconnect structure through a tungsten plug.

10. The image pixel sensor array as recited in claim 1, wherein the transparent electrode comprises indium tin oxide.

11. The image pixel sensor array as recited in claim 1, wherein the substrate comprises CMOS.

12. The image pixel sensor array as recited in claim 1, wherein the substrate comprises active circuits which sense charge accumulated by the image pixel sensors due to the image pixel sensors receiving light.

13. The image pixel sensor array as recited in claim 1, wherein the substrate comprises charge coupled devices.

14. The image pixel sensor array as recited in claim 1, wherein each pixel electrode comprises a P-layer.

15. The image pixel sensor array as recited in claim 14, wherein each image pixel sensor further comprises a separate N-layer section formed adjacent to the I-layer.

16. The image pixel sensor array as recited in claim 14, wherein each image pixel sensor further comprises a N-layer wherein the N-layer extends adjacently to a plurality of separate I-layers.