Borderless contact to diffusion with respect to gate conductor and methods for fabricating

• US 6,215,190 B1
• Filed: 05/12/1998
• Issued: 04/10/2001
• Est. Priority Date: 05/12/1998
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bruce, James Allen, Prxarik, John Joseph, Koburger, Charles W. III, Nakos, James Spiros, Rankin, Jed Hickory, Mann, Randy William, Peterson, Kirk David, Lercel, Michael James, Chapple-Sokol, Jonathan Daniel
• Primary Examiner(s): Lee, Eddie C.
• Assistant Examiner(s): Eckert, II, George C.
• Application Number:
  US09/076,525
• Time in Patent Office: 1,064 Days
• Field of Search: 257/369, 257/306, 257/640, 257/649, 257/774
• US Class Current: 257/774
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76888 By rendering at least a portion of the conductor non conductive, e.g. oxidation
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices

Abstract

A borderless contact to diffusion with respect to gate conductor is provided by employing a double insulating film stack as a mask for defining the gate conductor shapes for the entire chip and providing a relatively thin damage preventing layer on exposed conductive layer following defining the gate conductor shapes. In one embodiment, a borderless contact is provided by forming an insulating layer on a substrate, providing a conductive layer on the insulating layer, providing a second insulating layer on the conductive layer, providing a third insulating layer on the second insulating layer, removing preselected portions of the second and third insulating layers, providing a damage preventing layer in those areas where the second and third insulating layers have been removed, removing preselected portions of the third insulating layer, removing the damage preventing layer, removing exposed portions of the conductive layer, and removing now exposed portions of the second insulating layer.

Claims

1. A semiconductor structure comprising a semiconductor substrate;

conductive regions on said semiconductor substrate;

borderless contacts adjacent said conductive regions and said conductive regions having intermittent self-aligned insulating caps containing at least two layers of different material for providing the borderless contacts and having capless areas for contacting said conductive regions and wherein the self-aligned insulating caps are silicon nitride located above silicon dioxide.

2. The semiconductor structure of claim 1 wherein said conductive regions are of polycrystalline silicon.

3. The semiconductor structure of claim 1 wherein said semiconductor substrate is silicon.

4. The semiconductor structure of claim 1 wherein said conductive regions are conductive gates.

5. The semiconductor structure of claim 1 being conductive gates in an SRAM cell.

6. The semiconductor structure of claim 1 wherein said self-aligned insulating caps comprise a layer of silicon dioxide of about 500 Å

to about 1000 Å

beneath a layer of silicon nitride of about 1000 Å

to about 2000 Å

.

7. The semiconductor structure of claim 1 which further comprises self-aligned silicide located at said capless areas to contact said conductive regions.