Output stage for a memory device and for low voltage applications

• US 6,215,329 B1
• Filed: 07/23/1997
• Issued: 04/10/2001
• Est. Priority Date: 07/24/1996
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: SGS-Thomson Microelectronics, S.R.L. (STMicroelectronics NV)
• Inventors: Campardo, Giovanni, Zanardi, Stefano, Ghilardelli, Andrea
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Chang, Daniel D.
• Application Number:
  US08/899,228
• Time in Patent Office: 1,357 Days
• Field of Search: 326/88, 326/83, 326/82, 326/86, 326/17, 326/26, 326/27, 365/230.06, 365/230.08, 365/189.01, 365/189.11, 327/112, 327/390, 327/391, 327/589
• US Class Current: 326/88
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1069 I/O lines read out arrangements

Abstract

The present invention relates to an output stage for an electronic memory device and for low supply-voltage applications and is the type comprising a final stage of the pull-up/pull-down type made up of a complementary pair of transistors inserted between a primary reference supply voltage and a secondary reference voltage and a voltage regulator for the control terminals of said transistors. The regulator is a voltage booster using at least one bootstrap capacitor to increase the current flowing in the final stage by boosting the voltage applied to said control terminals.

Claims

1. An output sage for an electronic memory device and for low supply-voltage applications, the output stage, comprising:

a final stage of a pull-up/pull-down type made up of a pair of complementary transistors that are insertable between a primary reference supply voltage and a secondary reference voltage, each of the pair of complementary transistors having a control terminal; and

a voltage regulator having a respective output for the control terminal of each of the pair of complementary transistors, wherein the voltage regulator is a voltage booster using at least one bootstrap capacitor to increase a current flowing the final stage and raising an absolute value of a voltage applied to the control terminals;

wherein the pair of complementary transistors includes a first transistor and a second transistor, and wherein the voltage regulator includes;

a first circuit branch for the first transistor, the first circuit branch having;

a first input terminal that receives a first regulation signal,

a first delay element,

a first bootstrap capacitor, and

a first switch, wherein the first input terminal is coupled to the control terminal the first transistor through the first delay element, the first bootstrap capacitor and the first switch; and

a second circuit branch for the second transistor, the second circuit branch having;

a second input terminal that receives a second regulation signal,

a second delay element,

a second bootstrap capaitor, and

a second switch, wherein the second input terminal is coupled to the control terminal of the second transistor through the second delay element, the second bootstrap capacitor and the second switch;

wherein the first circuit branch further includes a third switch;

wherein the first bootstrap capacitor includes a first terminal connected to the first delay element, and a second terminal that couples to the secondary reference voltage through the third switch;

wherein the second terminal of the first bootstrap capacitor is farther coupled to the control terminal of the first transistor through the first switch;

wherein the second circuit branch further includes a fourth switch;

wherein the second bootstrap capacitor includes a first terminal connected to the second delay element, and a second terminal that couples to the reference supply voltage through the fourth switch; and

wherein the second terminal of the second bootstrap capacitor is further coupled to the control terminal of the second transistor through the second switch.

2. An output stage for an electronic memory device and for low supply-voltage applications, the output stage comprising:

a final stage of a pull-up/pull-down type made up of a pair of complementary transistors that are insertable between a primary reference supply voltage and a secondary reference voltage, each of the pair of complementary transistors having a control terminal; and

a voltage regulator having a respective output for the control terminal of each of the pair of complementary transistors, wherein the voltage regulator is a voltage booster using at least one bootstrap capacitor to increase a current flowing in the final stage and raising an absolute value of a voltage applied to the control terminals;

wherein the voltage regulator includes;

a first upper pair of selection transistors in series, a connection node formed between the first upper pair of selection transistors coinciding with an output of the voltage regulator;

a second lower pair of selection transistors in series, a connection node formed between the second lower pair of selection transistors coinciding with another output of the voltage regulator; and

a single bootstrap capacitor having a first terminal that connects to the reference supply voltage through the first upper pair of selection transistors, and a second terminal that connects to ground through the second lower pair of selection transistors.

3. The output stage of claim 2, wherein the selection transistors of the upper pair are complementary MOS type and have their drain terminals in common to form a first output terminal of the voltage regulator, and wherein each selection transistor of the upper pair has a gate terminal to receive a respective selection control signal.

4. The output stage of claim 2, wherein the selection transistors of the lower pair are the complementary MOS type and have their drain terminals in common to make up a second output terminal of the voltage regulator, and wherein each selection transistor of the lower pair has a gate terminal to receive a respective selection control signal.

5. The output stage of claim 4, wherein voltage regulator further includes:

a first upper drive transistor and a second upper drive transistor, wherein the first and second upper drive transistors have their drains terminals in common, wherein the first terminal of the bootstrap capacitor is further connected to the common drain terminals of the first and second upper drive transistors, wherein the first and second upper drive transistors are insertable in mutual series between the reference supply voltage and ground with the first upper drive transistor having a control terminal connected to an upper drive input terminal to receive a second lower selection signal.

6. The output stage of claim 5, wherein the voltage regulator further includes:

an upper switching transistor having a control terminal connected to the first terminal of the bootstrap capacitor, wherein the second upper drive transistor has a control terminal connected to a first internal circuit node that connects to ground through the upper switching transistor.

7. The output stage of claim 6, wherein the first upper driver transistor is a P-channel MOS transistor, and the upper switching transistor and the second upper driver transistor are N-channel MOS transistors.

8. The output stage of claim 6, wherein the voltage regulator further includes:

a first upper control transistor and a second upper control transistor having their drain terminals in common and connected to the first internal circuit node, wherein the first upper control transistor and the second upper control transistor have control terminals respectively connected to a first upper control terminal and a second upper control terminal, and wherein the first terminal of the bootstrap capacitor connects to the reference supply voltage through the first and second upper control transistors.

9. The output stage of claim 2, further comprising:

a switch designed to hold bulk terminals of P-channel MOS transistors at a voltage equal to a supply voltage when a voltage of the second terminal of the bootstrap capacitor is less than or equal to the supply voltage, wherein the switch establishes an electrical connection with the second terminal of the bootstrap capacitor only during a bootstrap phase of a pull-down transistor of the pair of complementary transistors.

10. The output stage of claim 9, wherein the switch holds bulk terminals of N-channel MOS transistors at a ground voltage value when a voltage of the first terminal of the bootstrap capacitor is greater than or equal to 0 volts, wherein the switch connects the bulk terminals of the N-channel MOS transistors to the first terminal of the bootstrap capacitor only during a bootstrap phase of a pull-up transistor of the pair of complementary transistors.

11. An output stage for an electronic memory device, comprising:

a final stage including;

a pull-up transistor having a first terminal that connects to a first voltage potential, a second terminal and control gate, and

a pull-down transistor having a first terminal connected to the second terminal of the pull-up transistor, a second terminal that connects to a ground potential, and a control gate; and

a voltage regulator having a first output coupled to the control gate of the pull-up transistor, a second output couled to the control gate of the pull-down transistor, and at least one bootstrap capacitor that provides, on the first output, a first voltage that is higher than the first voltage potential, and, on the second output, a second voltage that is lower than the ground potential;

wherein the at least one bootstrap capacitor has a first node coupled to the control gate of the pull-up transistor and a second node coupled to the control gate of the pull-down transistor.

12. The output stage of claim 11, wherein the voltage regulator includes a plurality of switches that operate to charge the at least one bootstrap capacitor during a charging phase, and to discharge the at least one bootstrap capacitor during a discharging phase to provide the first and second voltages.

13. The output stage of claim 11, wherein the voltage regulator includes a plurality of transistors having a plurality of respective bulk terminals, and wherein the output stage further comprises:

a switch circuit coupled to the voltage regulator, that holds at least one of the plurality of respective bulk terminals to the first voltage potential when a voltage at the first node exceeds a first predetermined voltage, and holds at least another of the plurality of respective bulk terminals to the ground potential when a voltage at the second node exceeds a second predetermined voltage.

14. An output stage for an electronic memory device, comprising:

a final stage including;

a pull-up transistor having a first terminal that connects to a first voltage potential, a second terminal and control gate, and

a pull-down transistor having a first terminal connected to the second terminal of the pull-up transistor, a second terminal that connects to a ground potential, and a control gate; and

means for providing a first voltage that is higher than the first voltage potential to the control gate of the pull-up transistor, and a second voltage that is lower than the ground potential to the control gate of the pull-down transistor;

wherein the means for providing includes a first node coupled to the control gate of the pull-up transistor and a second node coupled to the control gate of the pull-down transistor.

15. The output stage of claim 14, wherein the means for providing includes:

means for charging at least one capacitor during a charging phase, and discharging the at least one capacitor during a discharging phase to provide the first and second voltages.

16. The output stage of claim 14, wherein the means for providing further includes a plurality of transistors having a plurality of respective bulk terminals, and wherein the output stage further comprises:

a switch circuit coupled to the voltage regulator, that holds at least one of the plurality of respective bulk terminals to the first voltage potential when a voltage at the first node exceeds a first predetermined voltage, and holds at least another of the plurality of respective bulk terminals to the ground potential when a voltage at the second node exceeds a second predetermined voltage.

17. An output stage comprising:

an output circuit of the pull-up/pull-down type comprised of first and second complementary transistors that are disposed between a primary reference voltage and a secondary reference voltage;

each of said first and second complementary transistors having respective first and second control terminals;

first and second selection transistors;

a voltage booster having a first output connected by way of the first selection transistor to the control terminal of the pull-up transistor, and a second output connected by way of the second selection transistor to the control terminal of the pull-down transistor;

wherein said voltage booster comprises at least one bootstrap capacitor;

wherein the at least one bootstrap capacitor has a first node coupled to the first output of the voltage booster, and a second node coupled to the second output of the voltage booster.

18. The output stage according to claim 17 wherein the voltage booster includes a plurality of transistors having a plurality of respective bulk terminals, and wherein the output circuit further comprises:

a switch circuit coupled to the voltage booster, that holds at least one of the plurality of respective bulk terminals to the primary reference voltage when a voltage at the first node exceeds a first predetermined voltage, and holds at least another of the plurality of respective bulk terminals to the secondary reference voltage when a voltage at the second node exceeds a second predetermined voltage.

19. The output stage according to claim 17, wherein the voltage booster includes a plurality of switches that operate to charge the at least one bootstrap capacitor during a charging phase, and to discharge the at least one bootstrap capacitor during a discharging phase to provide the first and second voltages.

20. The output stage according to claim 17, wherein the first selection transistor biases the NMOS bulk terminals to a negative voltage value, which value is at a corresponding capacitor terminal, when the pull-up transistor is bootstrapped and to a reference value in all other cases.

21. The output stage according to claim 17, wherein the second selection transistor biases the PMOS bulk terminals to a voltage value higher than a supply voltage, which value is at the corresponding capacitor terminal, when the pull-down transistor is bootstrapped.

22. The output stage according to claim 17, wherein said first selection transistor is an N-channel transistor and said second selection transistor is a P-channel transistor.

23. The output stage according to claim 22, wherein said first selection transistor comprises a first upper pair of selection transistors connected in series and said second selection transistor comprises a second lower pair of selection transistors also connected in series.

24. The output stage according to claim 23, wherein a connection node formed between the transistors of the first pair couples to the control terminal of the pull-up transistor and the connection node formed between the transistors of the second pair of selection transistors couples to the control terminal of the pull-down transistor.

25. An output stage comprising:

an output circuit of the pull-up/pull-down type comprised of first and second complementary transistors that are disposed between a first voltage potential and a second voltage potential;

each of said first and second complementary transistors having respective first and second control terminals;

first and second selection transistors;

means for providing a first voltage that is higher than the first voltage potential by way of the first selection transistor to the first control terminal, and a second voltage that is lower than the second voltage potential by way of the second selection transistor to the second control terminal;

and wherein the means for providing includes means for charging at least one capacitor during a charging phase, and discharging the at least one capacitor during a discharging phase to provide the first and second voltages;

and wherein said at least one capacitor has first and second nodes connected to respective first and second voltages of said means for providing.

26. The output stage according to claim 25, wherein the means for providing further includes a plurality of transistors having a plurality of respective bulk terminals, and wherein the output stage further comprises:

a switch circuit coupled to the means for providing, that holds at least one of the plurality of respective bulk terminals to the first voltage potential when a voltage at the first node exceeds a first predetermined voltage, and holds at least another of the plurality of respective bulk terminals to the second voltage potential when a voltage at the second node exceeds a second predetermined voltage.