Method and apparatus for maximizing the random access bandwidth of a multi-bank DRAM in a computer graphics system

• US 6,215,497 B1
• Filed: 08/12/1998
• Issued: 04/10/2001
• Est. Priority Date: 08/12/1998
• Status: Expired due to Fees

• Current Assignee: Mosys Incorporated (Peraso, Inc.)
• Original Assignee: Monolithic System Technology
• Inventors: Leung, Wingyu
• Primary Examiner(s): Vo, Cliff N.
• Application Number:
  US09/133,475
• Time in Patent Office: 972 Days
• Field of Search: 345/418, 345/419, 345/503, 345/521, 345/512
• US Class Current: 345/419
• CPC Class Codes: G06T 1/60 Memory management

Abstract

A graphics sub-system having a 2-D graphics accelerator, a 3-D graphics accelerator and an embedded DRAM memory. The embedded DRAM memory serves as a frame buffer memory and/or a temporary storage memory for the 2-D graphics accelerator. The embedded DRAM memory also serves as a cache memory for the 3-D graphics accelerator or an external central processing unit (CPU). The embedded DRAM memory is logically divided into a plurality of independent banks, thereby resulting in a relatively fast average memory cycle time. More specifically, the embedded DRAM memory processes one transaction per clock cycle for accesses with no bank conflicts. The memory access time for any transaction (e.g., a bank-conflict access) is no greater than the memory cycle time plus the memory access time minus 1 clock cycle.

Claims

1. A graphics sub-system fabricated on a single chip comprising:

a 2-D graphics accelerator;

a 3-D graphics accelerator; and

an embedded dynamic random access memory (DRAM) coupled to the 2-D graphics accelerator and the 3-D graphics accelerator, wherein the embedded DRAM serves as a frame buffer memory or a temporary storage memory for the 2-D graphics accelerator, and wherein the embedded DRAM serves as a cache memory for the 3-D graphics accelerator.

2. The graphics sub-system of claim 1, further comprising:

a cache controller coupled to the 3-D graphics accelerator and the embedded DRAM;

a cache tag memory coupled to the cache controller; and

a comparator coupled to the cache tag memory and the cache controller.

3. The graphics sub-system of claim 1, further comprising a system interface for coupling the 2-D graphics accelerator and the 3-D graphics accelerator to an off-chip system memory.

4. The graphics sub-system of claim 1, further comprising a display controller, wherein the display controller is used by both the 2-D graphics accelerator and the 3-D graphics accelerator.

5. The graphics sub-system of claim 1, further comprising a memory controller coupled to the 3-D graphics accelerator, wherein the memory controller couples the 3-D graphics accelerator to an off-chip frame buffer memory.

6. The graphics sub-system of claim 1, wherein the embedded DRAM comprises a plurality of banks.

7. The graphics sub-system of claim 6, wherein each of the banks has a separate access control circuit.

8. The graphics sub-system of claim 6, wherein the number of banks is equal to or greater than the number of clock cycles per memory cycle, such that the embedded DRAM processes one transaction per clock cycle for accesses with no bank conflicts, and the maximum memory access time for any transaction is equal to memory cycle time plus the memory access time minus 1 clock cycle.

9. The graphics sub-system of claim 8, further comprising a posted write buffer having at least two entries.

10. The graphics sub-system of claim 8, further comprising a pre-fetched read buffer having at least two entries.

11. The graphics sub-system of claim 6, wherein the embedded DRAM further comprises a history buffer for storing a plurality of previously accessed bank addresses.

12. The graphics sub-system of claim 11, further comprising a plurality of comparators for comparing a current bank address with the each of the bank addresses stored in the history buffer.

13. A graphics sub-system fabricated on a single chip comprising:

a 3-D graphics accelerator;

a central processing unit (CPU) interface coupled to the 3-D graphics accelerator, wherein the CPU interface provides an interface between the graphics sub-system and an off-chip central processing unit (CPU); and

an embedded dynamic random access memory (DRAM) coupled to the 3-D graphics accelerator and the CPU interface, wherein the embedded DRAM serves as unified cache memory for the 3-D graphics accelerator and the CPU.

14. A graphics sub-system comprising an embedded dynamic random access memory (DRAM) having a number of banks equal to or greater than the number of clock cycles per memory cycle, so that the embedded DRAM processes one transaction per clock cycle for accesses with no bank conflicts and retires each transaction in the order of initiation.

15. The graphics sub-system of claim 14, wherein the maximum memory access time for any transaction is equal to memory cycle time plus the memory access time minus 1 clock cycle.

16. The graphics sub-system of claim 14, further comprising a posted write buffer having at least two entries.

17. The graphics sub-system of claim 14, further comprising a pre-fetched read buffer having at least two entries.

18. The graphics sub-system of claim 14, further comprising a read buffer and a write buffer.

19. A method of accessing a dynamic random access memory (DRAM) having a plurality of banks, the method comprising the steps of:

asserting an address and an address strobe signal to initiate a memory access to one of the banks;

comparing the address with a plurality of previously accessed addresses to determine whether the address will access the same bank as one of the previously accessed addresses, wherein the number of previously accessed addresses is selected to correspond to a number of clock cycles required for a memory cycle minus one; and

if the address will access the same bank as one of the previously accessed addresses, then asserting a control signal to indicate that the DRAM is not ready to receive any further memory accesses.

20. The method of claim 19, further comprising the step of delaying the access identified by the address if the address will access the same bank as one of the previously accessed addresses.

21. The method of claim 20, further comprising the step of selecting the length of the delay in response to which of the previously accessed addresses would provide access to the same bank as the address.

22. The method of claim 19, further comprising the step of updating the plurality of previously accessed addresses every clock cycle.