Methods of operating ferroelectric memory devices having reconfigurable bit lines

• US 6,215,693 B1
• Filed: 05/08/2000
• Issued: 04/10/2001
• Est. Priority Date: 12/13/1996
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: Jeon, Byung-gil, Chung, Yeon-bae
• Primary Examiner(s): Tran, Andrew
• Assistant Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US09/566,669
• Time in Patent Office: 337 Days
• Field of Search: 365/145, 365/210, 365/149, 365/202
• US Class Current: 365/145
• CPC Class Codes: G11C 11/22 using ferroelectric elements

Abstract

Integrated circuit memory devices contain a ferroelectric random access memory cell array and a ferroelectric reference cell array electrically coupled to a plurality of bit lines, a sense amplifier and a plate/bit line selection switch, coupled to the plurality of bit lines, for configuring selected bit lines as plate lines by selectively coupling first ones of the plurality of bit lines to the sense amplifier and by selectively coupling second ones of the plurality of bit lines to a plate line, in response to a column select signal. The inclusion of a selection switch and related driving circuits eliminates the need to provide extra dedicated plate lines because each of the bit lines can be at least temporarily configured as a plate line during reading and writing operations. The reference cell array also preferably comprises a plurality of ferroelectric reference cells which each comprise first and second access transistors therein and first and second ferroelectric capacitors therein which store complementary states. During a reading operation, the complementary data stored in the first and second ferroelectric reference capacitors is simultaneously provided to a portion of a first bit line which is electrically connected to a second input of a sense amplifier. Data in a memory cell within the array is also provided to another portion of the first bit line which is electrically connected to a first input of the sense amplifier. The sense amplifier is then activated to amplify a difference in potential between the different portions of the first bit line as complementary signals and then the signals are provided as output data.

Claims

1. In an integrated circuit memory device containing a data memory cell electrically connected between first and second upper bit lines, a reference circuit containing first and second reference memory cells electrically connected between first and second lower bit lines and a sense amplifier electrically coupled between the first upper and lower bit lines, a method of operating the memory device comprising the steps of:

reading the state of the data memory cell onto the first upper bit line;

reading the complementary states of the first and second reference memory cells simultaneously onto the first lower bit line; and

amplifying a difference in potential between the first upper bit line and first lower bit line.

2. In an integrated circuit memory device containing a data memory cell electrically connected between first and second upper bit lines, a reference circuit containing first and second reference memory cells electrically connected between first and second lower bit lines and a sense amplifier electrically coupled between the first upper and lower bit lines, a method of operating the memory device comprising the steps of:

reading the state of the data memory cell onto the first upper bit line;

reading the states of the first and second reference memory cells simultaneously onto the first lower bit line;

amplifying a difference in potential between the first upper bit line and first lower bit line; and

wherein said amplifying step is preceded by the steps of;

electrically isolating first and second portions of the second lower bit line from each other; and

electrically connecting the first lower bit line to the second portion of the second lower bit line to increase the effective capacitance of the first lower bit line.

3. The method of claim 2, wherein said amplifying step is followed by the step of restoring the states of the first and second reference memory cells.

4. The method of claim 3, wherein said step of reading the states of the first and second reference memory cells comprises reading the complementary states of the first and second reference memory cells simultaneously onto the first lower bit line.

5. The method of claim 2, wherein said step of reading the state of the data memory cell comprises applying a plate line voltage to the second upper bit line.

6. The method of claim 5, wherein said step of reading the states of the first and second reference memory cells comprises applying a plate line voltage to the first portion of the first lower bit line.

7. The method of claim 6, further comprising the step of writing the state of the data memory cell by applying data to the first upper bit line and applying a plate line voltage to the second upper bit line.

8. The method of claim 7, wherein said step of writing the state of the data memory cell comprises applying a plate line voltage to the second upper bit line after commencement of said step of applying data to the first upper bit line.

9. The method of claim 2, wherein said step of reading the state of the data memory cell comprises floating the first upper bit line and applying a plate line voltage to the second upper bit line.

10. The method of claim 9, wherein said step of reading the states of the first and second reference memory cells comprises floating the first lower bit line and applying a plate line voltage to the first portion of the first lower bit line.

11. The method of claim 2, wherein the first and second reference memory cells comprise first and second ferroelectric reference capacitors which are electrically connected to the first portion of the second lower bit line;

and wherein said restoring step comprises disposing the first ferroelectric reference capacitor in a first polarization state and then disposing the second ferroelectric capacitor in a second polarization state, opposite the first polarization state, by applying a plate line voltage to the first portion of the second lower bit line.

12. In an integrated circuit memory device containing a data memory cell electrically connected between first and second upper bit lines, a reference circuit containing first and second reference memory cells electrically connected between first and second lower bit lines and a sense amplifier electrically coupled between the first upper and lower bit lines, a method of operating the memory device comprising the steps of:

reading the state of the data memory cell onto the first upper bit line;

reading the states of the first and second reference memory cells simultaneously onto the first lower bit line;

amplifying a difference in potential between the first upper bit line and first lower bit line; and

writing the state of the data memory cell by applying data to the first upper bit line and applying a plate line voltage to the second upper bit line.

13. The method of claim 12, wherein said step of writing the state of the data memory cell comprises applying a plate line voltage to the second upper bit line after commencement of said step of applying data to the first upper bit line.