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Circuit and method for eliminating idle cycles in a memory device

  • US 6,215,724 B1
  • Filed: 03/14/2000
  • Issued: 04/10/2001
  • Est. Priority Date: 09/16/1997
  • Status: Expired due to Term
First Claim
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1. A method of operating a memory device, comprising:

  • latching a first address into a first write address register prior to a first clock cycle;

    latching data associated with the first address from a data bus of the memory device into a first data input register prior to the first clock cycle;

    reading data associated with a second address from a memory array of the memory device during the first clock cycle;

    providing the first address to the memory array from the first write address register during a second clock cycle immediately subsequent to the first clock cycle; and

    writing the data associated with the first address to the memory array from the first data input register during the second clock cycle.

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