Adaptive analog equalizer for partial response channels

• US 6,216,148 B1
• Filed: 11/12/1998
• Issued: 04/10/2001
• Est. Priority Date: 11/12/1998
• Status: Expired due to Term

• Current Assignee: Maxtor Corporation (Seagate Technology Holdings Plc)
• Original Assignee: Quantum Corporation (Chi Ko Investment Co., Ltd.)
• Inventors: Moran, Patrick J., Chan, Ivan Tin-Yam, Han, Ke
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US09/191,249
• Time in Patent Office: 880 Days
• Field of Search: 708/819, 708/3, 708/322-323, 708/320, 375/232-233, 360/65
• US Class Current: 708/819
• CPC Class Codes: G11B 20/10009 Improvement or modification of read or write signals
• CPC Class Codes: G11B 20/10046 filtering or equalising, e.g. setting the tap weights of an FIR filter
• CPC Class Codes: G11B 2020/10944 Real-time recording or reproducing, e.g. for ensuring seamless playback of AV data

Abstract

A single analog filter structure within a partial response channel combines an antialias low pass filter and a time domain waveform shaping equalizer upstream of a digital sampler. The filter also improves latencies associated with timing acquisition of a sampler clock generator loop by removing the latency of a separate equalization filter. The filter also provides a method for adapting a combination of internal filter state voltages and currents in real time for optimizing pole locations of the analog filter structure, during both data and timing recovery operations of the channel.

Claims

1. An n^th order analog low pass and channel response equalization filter within a sampled digital partial response channel including a clocked analog-to-digital converter, wherein n lies in a range between 5 and 12, the filter comprising:

a plurality of adaptable transconductance stages connected in a feedback arrangement,

means for establishing an optimized filter pole location of each stage, and

feedback control loop means for adapting a filter zero location of a said stage on the basis of gradients from said stage.

2. The analog low pass and channel response equalization filter set forth in claim 1 wherein the multiple stages are interconnected into a follow-the-leader-feadback filter topology.

3. The analog low pass and channel response equalization filter set forth in claim 1 wherein the means for establishing an optimized filter pole location comprises a register for holding digital filter pole location values, and a digital-to-analog converter for converting the digital filter pole location values into analog pole control signals which are applied to control the transconductance stages.

4. The analog low pass and channel response equalization filter set forth in claim 1 wherein the means for adapting a filter zero location of each stage comprises means for deriving a least-mean-squared error approximation which minimizes time averaged error between expected sample values and actual sample values put out by the clocked analog-to-digital converter.

5. The analog low pass and channel response equalization filter set forth in claim 4 wherein the means for adapting a filter zero location generates a digital tap control value, and wherein each stage comprises at least one tap and a digital-to-analog converter for convering the digital tap control value into a tap control level applied to the tap.

6. The filter of claim 1, wherein the plurality of adaptable transconductance stages include at least one stage comprising:

integrating amplifier means for integrating an incoming signal;

a slave transconductance cell including;

a differential transistor pair Q3-Q4; and

a slave field effect transistor bridging emitter electrodes of the transistor pair Q3-Q4;

a control element of the slave field effect transistor responsive to a control voltage, the slave transconductance cell providing a stage output;

a digital-to-analog converter U1 for converting a digital stage adaptation value into a differential tuning current;

a master transconductance cell including;

a differential transistor pair Q5-Q6 connected to receive the differential timing current; and

a master field effect transistor bridging emitter electrodes of the transistor pair Q5-Q6, a control element of the master field effect transistor responsive to the control voltage; and

a servo amplifier S1 responsive to the differential tuning current for generating the control voltage.

7. An adaptive analog filter in a partial response channel including a voltage controlled amplifier and a clocked analog to digital converter, the channel further including a digital data bit detector means for detecting data bits from unfiltered digital samples put out by the clocked analog to digital converter, the adaptive analog filter further comprising:

a plurality of analog transconductance/capacitance stages, at least some of the stages putting out gradient voltages and receiving analog tap control signals for adjusting stage capacitance,

a digital error generator connected to generate discrete error values by comparing functions of detected data bits and unfiltered digital samples,

a digital least mean squared error generator for generating tap control values from the discrete error values and from digital representations of the gradient voltages, and

digital to analog converter means for converting the tap control values to the analog tap control signals.

8. The adaptive analog filter set forth in claim 7 wherein the plurality of stages are connected in tandem in a follow-the-leader filter topology, and wherein at least some of the stages have feedback paths to prior stages.

9. The adaptive analog filter set forth in claim 7 wherein the plurality of stages are connected in parallel and further comprising summing junction for summing outputs of the stages.

10. The adaptive analog filter set forth in claim 7 wherein the digital least mean squared error generator includes a gain register for holding a loop gain value, and wherein the digital least mean squared error generator generates tap control values as functions of the discrete error values, digital representations of the gradient voltages and loop gain value.

11. The adaptive analog filter set forth in claim 7 wherein during processing of a single frequency timing pattern the digital error generator generates discrete timing error signals and the digital least mean squared error generator generates timing tap control values for adapting the filter to a predetermined timing band pass spectrum during processing of the timing pattern, and further comprising sample clock generation circuitry for generating a sample clock in response to the discrete error signals.

12. The adaptive analog filter set forth in claim 11 wherein the sample clock generation circuitry comprises a timing pattern zero crossing detector for generating a timing window, and a phase locked loop responsive to the timing window and including a voltage controlled oscillator for generating the sample clock responsive to a nominal frequency and the timing window.

13. The adaptive analog filter set forth in claim 12 wherein the sample clock generation circuitry further comprises a phase error detector for detecting a timing phase errors in digital samples put out by the clocked analog to digital converter and for providing the phase errors to the phase locked loop.

14. The adaptive analog filter set forth in claim 7 wherein the partial response channel is formed as a single mixed signal analog/digital integrated circuit chip.

15. The adaptive analog filter set forth in claim 7 wherein the digital error generator comprises a digital filter connected to receive data bits from the digital data bit detector means for putting out filtered reference values, a delay matching circuit connected to the clocked analog to digital converter for matching digital processing delays through the digital data bit detector means and the digital filter and providing a delayed raw data output, and a digital combining means for combining the filtered reference values with the delayed raw data output to provide the discrete error values.

16. The adaptive analog filter set forth in claim 7 wherein the digital least mean squared error generator comprises a multiplexer having direct and inverting inputs for receiving the discrete error values and a multiplexer output, and a control input controlled by delay matched sign values derived from said gradient voltages, a multiplier connected to multiply values from the multiplexer output by gain values to produce products, and a digital integrator means for integrating the product to produce said tap control values.

17. The adaptive analog filter set forth in claim 16 wherein the digital integrator includes a digital summing circuit and integrator register, wherein the digital summing circuit sums the products with values fed back from an output of the register to produce sums held in the register.

18. The adaptive analog filter set forth in claim 16 further comprising an initial tap register connected to supply initial tap values to the integrator register.

19. The filter of claim 7, wherein the plurality of adaptable transconductance stages include at least one stage comprising:

integrating amplifier means for integrating an incoming signal;

a slave transconductance cell including;

a differential transistor pair Q3-Q4; and

a slave field effect transistor bridging emitter electrodes of the transistor pair Q3-Q4;

a control element of the slave field effect transistor responsive to a control voltage, the slave transconductance cell providing a stage output;

a digital-to-analog converter U1 for converting a digital stage adaptation value into a differential tuning current;

a master transconductance cell including;

a differential transistor pair Q5-Q6 connected to receive the differential timing current; and

a master field effect transistor bridging emitter electrodes of the transistor pair Q5-Q6, a control element of the master field effect transistor responsive to the control voltage; and

a servo amplifier S1 responsive to the differential tuning current for generating the control voltage.

20. The filter of claim 19, wherein the at least one stage further comprises a buffer stage B1 between the integrating amplifier means and the slave transconductance cell.