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Integrated circuit design using a frequency synthesizer that automatically ensures testability

  • US 6,216,254 B1
  • Filed: 12/16/1998
  • Issued: 04/10/2001
  • Est. Priority Date: 12/16/1998
  • Status: Expired due to Term
First Claim
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1. An improved integrated circuit comprising a frequency synthesizer, a master reset input and a function circuit, the frequency synthesizer comprising a plurality of frequency outputs for outputting a plurality of output frequency signals generated from a reference frequency at a reference frequency input, the frequency synthesizer being operable to generate a lock signal to indicate that one of the output frequency signals is synchronous to the reference frequency, the master reset input being coupled to a reset signal source for receiving a master reset signal to initialize the integrated circuit, the function circuit comprising a function reset input for receiving a function reset signal, and a plurality of frequency inputs for receiving at least one of the plurality of output frequency signals from the frequency synthesizer, the improvement comprising:

  • a testability circuit having a test mode for testing the integrated circuit, the testability circuit comprising;

    a reset input for receiving the master reset signal; and

    a reset controller for coupling a reset out signal to the function reset input when in the test mode, when the frequency synthesizer generates the lock signal and when the master reset signal is received;

    a select input for receiving a select signal, the select signal being operable to indicate an at-speed test mode such that the testability circuit is in the test mode and a system mode such that the integrated circuit is in a normal operating mode, wherein the reset controller couples, when the system mode is selected, the master reset signal to the function reset input, wherein the function circuit includes a clock input for receiving a clock out signal; and

    wherein;

    the testability circuit includes;

    a second select input for selecting a static test mode; and

    a clock controller for generating the clock out signal, the clock signal being generated from one of the output frequency signals of the frequency synthesizer when the at-speed test mode and the system mode is selected, and from the reference frequency when the static test mode is selected.

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