Integrated circuit design using a frequency synthesizer that automatically ensures testability

• US 6,216,254 B1
• Filed: 12/16/1998
• Issued: 04/10/2001
• Est. Priority Date: 12/16/1998
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Kuppinger, Jonathan P., Pesce, Michael S., Gearhardt, Kevin J.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Speight, Jibreel
• Application Number:
  US09/212,769
• Time in Patent Office: 846 Days
• Field of Search: 377/47, 375/327, 714/733, 455/226.1
• US Class Current: 716/136
• CPC Class Codes: G01R 31/31701 Arrangements for setting the Unit Under Test [UUT] in a test mode

Abstract

A system for designing integrated circuits that use frequency synthesizers to ensure testability. A testability circuit is added or connected to the frequency synthesizer that will receive allow the integrated circuit to operate in a system mode for normal function and in a test mode during testing. In the test mode, the testability circuit will inhibit the reset signal from initializing the integrated circuit until the frequency synthesizer has reached phase lock. The testability circuit may be implemented as a component in the frequency synthesizer cell in an ASIC design system such that anytime the frequency synthesizer is used, the integrated circuit is testable.

Claims

1. An improved integrated circuit comprising a frequency synthesizer, a master reset input and a function circuit, the frequency synthesizer comprising a plurality of frequency outputs for outputting a plurality of output frequency signals generated from a reference frequency at a reference frequency input, the frequency synthesizer being operable to generate a lock signal to indicate that one of the output frequency signals is synchronous to the reference frequency, the master reset input being coupled to a reset signal source for receiving a master reset signal to initialize the integrated circuit, the function circuit comprising a function reset input for receiving a function reset signal, and a plurality of frequency inputs for receiving at least one of the plurality of output frequency signals from the frequency synthesizer, the improvement comprising:

a testability circuit having a test mode for testing the integrated circuit, the testability circuit comprising;

a reset input for receiving the master reset signal; and

a reset controller for coupling a reset out signal to the function reset input when in the test mode, when the frequency synthesizer generates the lock signal and when the master reset signal is received;

a select input for receiving a select signal, the select signal being operable to indicate an at-speed test mode such that the testability circuit is in the test mode and a system mode such that the integrated circuit is in a normal operating mode, wherein the reset controller couples, when the system mode is selected, the master reset signal to the function reset input, wherein the function circuit includes a clock input for receiving a clock out signal; and

wherein;

the testability circuit includes;

a second select input for selecting a static test mode; and

a clock controller for generating the clock out signal, the clock signal being generated from one of the output frequency signals of the frequency synthesizer when the at-speed test mode and the system mode is selected, and from the reference frequency when the static test mode is selected.

2. An integrated circuit as claimed in claim 1 wherein the clock controller comprises:

a multiplexer to switch one of the output frequency signals to the clock input on the function circuit when the system mode and the at-speed mode is selected, and to switch the reference frequency to the clock input when the static test mode is selected.

3. An improved integrated circuit comprising a frequency synthesizer, a master reset input and a function circuit, the frequency synthesizer comprising a plurality of frequency outputs for outputting a plurality of output frequency signals generated from a reference frequency at a reference frequency input, the frequency synthesizer being operable to generate a lock signal to indicate that one of the output frequency signals is synchronous to the reference frequency, the master reset input being coupled to a reset signal source for receiving a master reset signal to initialize the integrated circuit, the function circuit comprising a function reset input for receiving a function reset signal, and a plurality of frequency inputs for receiving at least one of the plurality of output frequency signals from the frequency synthesizer, the improvement comprising:

a testability circuit having a test mode for testing the integrated circuit, the testability circuit comprising;

a reset input for receiving the master reset signal; and

a reset controller for coupling a reset out signal to the function reset input when in the test mode, when the frequency synthesizer generates the lock signal and when the master reset signal is received, wherein the reset controller comprises;

a reset triggering circuit having first input for the master reset and a second input for the lock signal, the reset triggering circuit being operable to switch the master reset to lock reset signal when the lock signal is received; and

a multiplexer for switching the master reset as the reset out signal when the system mode is selected and for switching the lock reset signal as the reset out signal when the at-speed test mode is selected.

4. An improved system for designing an integrated circuit comprising a plurality of design blocks, a plurality of design connections and a design block connector, the design blocks being computer representations for circuits having selected functions, the design connections being computer representations of conductor connections between the design blocks and of integrated circuit inputs and outputs, the design block connector comprising a user interface responsive to user commands to connect the design blocks to design the integrated circuit, at least one of the design blocks being a function block for representing a function circuit, another one of the design blocks being a frequency synthesizer block for representing a frequency synthesizer, the frequency synthesizer comprising a plurality of frequency outputs for outputting a plurality of output frequency signals generated from a reference frequency at a reference frequency input, the frequency synthesizer being operable to generate a lock signal to indicate that one of the output frequency signals is synchronous to the reference frequency, the design connections including a master reset signal to initialize the integrated circuit and a function reset input for resetting the function circuit, the improvement comprising:

a testability circuit having a test mode for testing the integrated circuit, the testability circuit comprising;

a reset input for receiving the master reset signal; and

a reset controller for coupling a reset out signal to the function reset input, when in the test mode, the frequency synthesizer generates the lock signal and the master reset signal is received;

wherein the integrated circuit designed by the user is manufactured from the connected design blocks and is testable when the integrated circuit includes the frequency synthesizer block, wherein the testability circuit further comprises;

a select input for receiving a select signal, the select signal being operable to indicate an at-speed test mode such that the testability circuit is in the test mode and a system mode such that the integrated circuit is in a normal operating mode, wherein the reset controller couples, when the system mode is selected, the master reset signal to the function reset input, and wherein;

the function circuit includes a clock input for receiving a clock signal; and

wherein;

the testability circuit includes;

a second select input for selecting a static test mode; and

a clock controller for generating the clock signal, the clock signal being generated from one of the output frequency signals of the frequency synthesizer when the at-speed test mode and the system mode is selected, and from the reference frequency when the static test mode is selected.

5. An improved system for designing an integrated circuit comprising a plurality of design blocks, a plurality of design connections and a design block connector, the design blocks being computer representations for circuits having selected functions, the design connections being computer representations of conductor connections between the design blocks and of integrated circuit inputs and outputs, the design block connector comprising a user interface responsive to user commands to connect the design blocks to design the integrated circuit, at least one of the design blocks being a function block for representing a function circuit, another one of the design blocks being a frequency synthesizer block for representing a frequency synthesizer, the frequency synthesizer comprising a plurality of frequency outputs for outputting a plurality of output frequency signals generated from a reference frequency at a reference frequency input, the frequency synthesizer being operable to generate a lock signal to indicate that one of the output frequency signals is synchronous to the reference frequency, the design connections including a master reset signal to initialize the integrated circuit and a function reset input for resetting the function circuit, the improvement comprising:

a testability circuit having a test mode for testing the integrated circuit, the testability circuit comprising;

a reset input for receiving the master reset signal; and

a reset controller for coupling a reset out signal to the function reset input, when in the test mode, the frequency synthesizer generates the lock signal and the master reset signal is received;

wherein the integrated circuit designed by the user is manufactured from the connected design blocks and is testable when the integrated circuit includes the frequency synthesizer block wherein the testability circuit further comprises;

a select input for receiving a select signal, the select signal being operable to indicate an at-speed test mode such that the testability circuit is in the test mode and a system mode such that the integrated circuit is in a normal operating mode, wherein the reset controller couples, when the system mode is selected, the master reset signal to the function reset input, and wherein the clock controller comprises;

a multiplexer to switch one of the output frequency signals to the clock input on the function circuit when the system mode and the at-speed mode is selected, and to switch the reference frequency to the clock input when the static test mode is selected.

6. An improved system for designing an integrated circuit comprising a plurality of design blocks, a plurality of design connections and a design block connector, the design blocks being computer representations for circuits having selected functions, the design connections being computer representations of conductor connections between the design blocks and of integrated circuit inputs and outputs, the design block connector comprising a user interface responsive to user commands to connect the design blocks to design the integrated circuit, at least one of the design blocks being a function block for representing a function circuit, another one of the design blocks being a frequency synthesizer block for representing a frequency synthesizer, the frequency synthesizer comprising a plurality of frequency outputs for outputting a plurality of output frequency signals generated from a reference frequency at a reference frequency input, the frequency synthesizer being operable to generate a lock signal to indicate that one of the output frequency signals is synchronous to the reference frequency, the design connections including a master reset signal to initialize the integrated circuit and a function reset input for resetting the function circuit, the improvement comprising:

a testability circuit having a test mode for testing the integrated circuit, the testability circuit comprising;

a reset input for receiving the master reset signal; and

a reset controller for coupling a reset out signal to the function reset input, when in the test mode, the frequency synthesizer generates the lock signal and the master reset signal is received;

wherein the integrated circuit designed by the user is manufactured from the connected design blocks and is testable when the integrated circuit includes the frequency synthesizer block, wherein the reset controller comprises;

a reset triggering circuit having first input for the master reset and a second input for the lock signal, the reset triggering circuit being operable to switch the master reset to a lock reset signal when the lock signal is received; and

a multiplexer for switching the master reset as the reset out signal when the system mode is selected and for switching the lock reset signal as the reset out signal when the at-speed mode is selected.

7. A method for ensuring testability of an integrated circuit comprising a function circuit for performing integrated circuit functions and a frequency synthesizer for generating at least one operating frequency used by the function circuit, the method comprising the steps of:

coupling a testability circuit to a frequency synthesizer by the steps of;

coupling a lock signal output from the frequency synthesizer to the testability circuit for communicating a lock signal to the testability circuit, the lock signal indicating a phase lock in the frequency synthesizer;

coupling an operating frequency output to the testability circuit; and

coupling a reference frequency input to the frequency synthesizer and to the testability circuit;

coupling a master reset signal input for receiving a master reset signal that resets the integrated circuit to the testability circuit;

coupling a clock signal output from the testability circuit to the function circuit;

coupling a reset output from the testability circuit to the function circuit; and

coupling a mode selector to select a test mode, the test mode being operable to permit testing of the integrated circuit by inhibiting the reset signal from the reset output until the lock signal is received from the frequency synthesizer and the master reset signal is received at the master reset signal input, wherein the step of coupling the mode selector further comprises the steps of;

switching a first multiplexer to receive the operating frequency from the frequency synthesizer;

switching a second multiplexer to receive a lock signal from the frequency synthesizer; and

triggering a reset controller to couple the reset signal to the function circuit when the master reset signal and the lock signal are received.

8. An integrated circuit comprising a frequency synthesizer, a master reset input and a function circuit, the frequency synthesizer comprising a plurality of frequency outputs for outputting a plurality of output frequency signals generated from a reference frequency at a reference frequency input, the frequency synthesizer being operable to generate a lock signal to indicate that one of the output frequency signals is synchronous to the reference frequency, the master reset input being coupled to a reset signal source for receiving a master reset signal to initialize the integrated circuit, the function circuit comprising a function reset input for receiving a function reset signal, and a plurality of frequency inputs for receiving at least one of the plurality of output frequency signals from the frequency synthesizer, said integrated circuit including a testability circuit having a test mode for testing the integrated circuit, said testability circuit configured to couple a reset out signal to the function reset input when in the test mode, when the frequency synthesizer generates the lock signal and when the master reset signal is received, said testability circuit configured to receive a select signal operable to indicate an at-speed test mode such that the testability circuit is in the test mode and a system mode such that the integrated circuit is in a normal operating mode, wherein the testability circuit couples, when the system mode is selected, the master reset signal to the function reset input, wherein the function circuit includes a clock input for receiving a clock out signal;

and wherein the testability circuit includes a second select input for selecting a static test mode and is configured to generate the clock out signal, the clock signal being generated from one of the output frequency signals of the frequency synthesizer when the at-speed test mode and the system mode is selected, and from the reference frequency when the static test mode is selected.

9. An integrated circuit as claimed in claim 8, wherein said testability circuit is configured to switch one of the output frequency signals to the clock input on the function circuit when the system mode and the at-speed mode is selected, and to switch the reference frequency to the clock input when the static test mode is selected.

10. An integrated circuit comprising a frequency synthesizer, a master reset input and a function circuit, the frequency synthesizer comprising a plurality of frequency outputs for outputting a plurality of output frequency signals generated from a reference frequency at a reference frequency input, the frequency synthesizer being operable to generate a lock signal to indicate that one of the output frequency signals is synchronous to the reference frequency, the master reset input being coupled to a reset signal source for receiving a master reset signal to initialize the integrated circuit, the function circuit comprising a function reset input for receiving a function reset signal, and a plurality of frequency inputs for receiving at least one of the plurality of output frequency signals from the frequency synthesizer, said integrated circuit including a testability circuit having a test mode for testing the integrated circuit, the testability circuit configured to couple a reset out signal to the function reset input when in the test mode, when the frequency synthesizer generates the lock signal and when the master reset signal is received, said testability circuit configured to selectively operate in a system mode and an at-speed test mode, said testability circuit configured to switch the master reset to lock reset signal when the lock signal is received and configured to switch the master reset as the reset out signal when the system mode is selected, said testability circuit configured to switch the lock reset signal as the reset out signal when the at-speed test mode is selected.

11. A system for designing an integrated circuit comprising a plurality of design blocks, a plurality of design connections and a design block connector, the design blocks being computer representations for circuits having selected functions, the design connections being computer representations of conductor connections between the design blocks and of integrated circuit inputs and outputs, the design block connector comprising a user interface responsive to user commands to connect the design blocks to design the integrated circuit, at least one of the design blocks being a function block for representing a function circuit, another one of the design blocks being a frequency synthesizer block for representing a frequency synthesizer, the frequency synthesizer comprising a plurality of frequency outputs for outputting a plurality of output frequency signals generated from a reference frequency at a reference frequency input, the frequency synthesizer being operable to generate a lock signal to indicate that one of the output frequency signals is synchronous to the reference frequency, the design connections including a master reset signal to initialize the integrated circuit and a function reset input for resetting the function circuit, said system including a testability circuit having a test mode for testing the integrated circuit, the testability circuit configured to receive the master reset signal and couple a reset out signal to the function reset input, when in the test mode, the frequency synthesizer generates the lock signal and the master reset signal is received, wherein the integrated circuit designed by the user is manufactured from the connected design blocks and is testable when the integrated circuit includes the frequency synthesizer block, said testability circuit configured to receive a select signal operable to indicate an at-speed test mode such that the testability circuit is in the test mode and a system mode such that the integrated circuit is in a normal operating mode, wherein the testability circuit couples, when the system mode is selected, the master reset signal to the function reset input, wherein the function circuit is configured to receive a clock signal and the testability circuit includes a second select input for selecting a static test mode and is configured to generate the clock signal from one of the output frequency signals of the frequency synthesizer when the at-speed test mode and the system mode is selected, and from the reference frequency when the static test mode is selected.

12. A system for designing an integrated circuit comprising a plurality of design blocks, a plurality of design connections and a design block connector, the design blocks being computer representations for circuits having selected functions, the design connections being computer representations of conductor connections between the design blocks and of integrated circuit inputs and outputs, the design block connector comprising a user interface responsive to user commands to connect the design blocks to design the integrated circuit, at least one of the design blocks being a function block for representing a function circuit, another one of the design blocks being a frequency synthesizer block for representing a frequency synthesizer, the frequency synthesizer comprising a plurality of frequency outputs for outputting a plurality of output frequency signals generated from a reference frequency at a reference frequency input, the frequency synthesizer being operable to generate a lock signal to indicate that one of the output frequency signals is synchronous to the reference frequency, the design connections including a master reset signal to initialize the integrated circuit and a function reset input for resetting the function circuit, the system including a testability circuit having a test mode for testing the integrated circuit, the testability circuit configured to receive the master reset signal and configured to couple a reset out signal to the function reset input, when in the test mode, the frequency synthesizer generates the lock signal and the master reset signal is received, wherein the integrated circuit designed by the user is manufactured from the connected design blocks and is testable when the integrated circuit includes the frequency synthesizer block, wherein the testability circuit is configured to receive a select signal operable to indicate an at-speed test mode such that the testability circuit is in the test mode and a system mode such that the integrated circuit is in a normal operating mode, wherein the reset controller couples, when the system mode is selected, the master reset signal to the function reset input, and wherein the testability circuit is configured to switch one of the output frequency signals to the clock input on the function circuit when the system mode and the at-speed mode is selected, and to switch the reference frequency to the clock input when the static test mode is selected.

13. A system for designing an integrated circuit comprising a plurality of design blocks, a plurality of design connections and a design block connector, the design blocks being computer representations for circuits having selected functions, the design connections being computer representations of conductor connections between the design blocks and of integrated circuit inputs and outputs, the design block connector comprising a user interface responsive to user commands to connect the design blocks to design the integrated circuit, at least one of the design blocks being a function block for representing a function circuit, another one of the design blocks being a frequency synthesizer block for representing a frequency synthesizer, the frequency synthesizer comprising a plurality of frequency outputs for outputting a plurality of output frequency signals generated from a reference frequency at a reference frequency input, the frequency synthesizer being operable to generate a lock signal to indicate that one of the output frequency signals is synchronous to the reference frequency, the design connections including a master reset signal to initialize the integrated circuit and a function reset input for resetting the function circuit, the system including a testability circuit having a test mode for testing the integrated circuit, the testability circuit configured to receive the master reset signal and couple a reset out signal to the function reset input, when in the test mode, the frequency synthesizer generates the lock signal and the master reset signal is received;

wherein the integrated circuit designed by the user is manufactured from the connected design blocks and is testable when the integrated circuit includes the frequency synthesizer block, wherein the testability circuit is configured to receive the master reset and the lock signal and is operable to switch the master reset to a lock reset signal when the lock signal is received and is configured to switch the master reset as the reset out signal when the system mode is selected and for switching the lock reset signal as the reset out signal when the at-speed mode is selected.

14. A method for ensuring testability of an integrated circuit comprising a function circuit for performing integrated circuit functions and a frequency synthesizer for generating at least one operating frequency used by the function circuit, the method comprising the steps of:

coupling a testability circuit to a frequency synthesizer by the steps of;

coupling a lock signal output from the frequency synthesizer to the testability circuit for communicating a lock signal to the testability circuit, the lock signal indicating a phase lock in the frequency synthesizer;

coupling an operating frequency output to the testability circuit; and

coupling a reference frequency input to the frequency synthesizer and to the testability circuit;

coupling a master reset signal input for receiving a master reset signal that resets the integrated circuit to the testability circuit;

coupling a clock signal output from the testability circuit to the function circuit;

coupling a reset output from the testability circuit to the function circuit; and

coupling a mode selector to select a test mode, the test mode being operable to permit testing of the integrated circuit by inhibiting the reset signal from the reset output until the lock signal is received from the frequency synthesizer and the master reset signal is received at the master reset signal input, wherein the step of coupling the mode selector further comprises the steps of;

receiving the operating frequency from the frequency synthesizer;

receiving a lock signal from the frequency synthesizer; and

coupling the reset signal to the function circuit when the master reset signal and the lock signal are received.