Computer-aided logic circuit designing apparatus computer-aided logic circuit designing system, and computer-aided logic circuit designing method

• US 6,216,255 B1
• Filed: 02/26/1998
• Issued: 04/10/2001
• Est. Priority Date: 07/28/1997
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Komatsu, Shinpei, Kubono, Chika, Kirinaka, Masaki, Tobita, Tatsushi, Ito, Yasushi
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Kik, Phallaka
• Application Number:
  US09/030,859
• Time in Patent Office: 1,139 Days
• Field of Search: 395/500-2-5, 395/500-5-5, 716/1-21, 703/14, 703/17, 703/19
• US Class Current: 716/103
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/3312 Timing analysis

Abstract

A computer-aided logic circuit designing apparatus in which data on a plurality of circuits is stored in a database, the data on a plurality of circuits is read out therefrom and combined by a net list-RTL description combining section, a clock system portion is analyzed based on the logic circuit obtained by combining the data by a clock system analyzing section, and a result of the analysis is displayed by an analysis result display section correlating each type of clock system to a corresponding clock input element.

Claims

1. A computer-aided logic circuit designing apparatus designing a logic circuit by integrating data on circuits comprising:

a combining unit combining data on circuits into a combined circuit, each of the circuits having a clock system portion;

a clock system analyzer analyzing clock system portions of the combined circuit by differentiating clock systems in said combined circuit; and

an analysis result display unit displaying a result of the analysis of the combined circuit with the clock systems of the combined circuit differentiated from each other.

2. A computer-aided logic circuit designing apparatus according to claim 1 further comprising:

a correcting unit correcting said data on circuits based on the result of analysis displayed by said analysis result display unit.

3. A computer-aided logic circuit designing apparatus according to claim 1, wherein said clock system analyzer extracts an asynchronous circuit portion from said combined circuit through analysis of a clock system, and said analysis result display unit generates, when displaying said result of analysis, an alarm concerning the asynchronous circuit portion extracted by said clock system analyzer.

4. A computer-aided logic circuit designing apparatus according to claim 1, wherein said clock system analyzer obtains said analysis result in which data for types of clock system, data on clock input elements, and data for warning of troubles in clock systems are correlated to each other.

5. A computer-aided logic circuit designing apparatus designing a logic circuit by integrating data on circuits comprising:

a combining unit combining data on circuits into a combined circuit, each of the circuits having one or more clock input elements, each of the clock input elements constituting a clock system portion;

a clock system analyzer analyzing clock system portions of the combined circuit by differentiating clock systems in said combined circuit; and

an analysis result display unit displaying a result of the analysis of the combined circuit with the clock systems of the combined circuit differentiated from each other.

6. A computer-aided logic circuit designing apparatus according to claim 5 further comprising:

a correcting unit correcting said data on circuits based on the result of analysis displayed by said analysis result display unit.

7. A computer-aided logic circuit designing apparatus according to claim 5, wherein said clock system analyzer extracts an asynchronous circuit portion from said combined circuit through analysis of a clock system, and said analysis result display unit generates, when displaying said result of analysis, an alarms concerning the asynchronous circuit portion extracted by said clock system analyzer.

8. A computer-aided logic circuit designing apparatus designing a logic circuit by integrating data on circuits comprising:

a storage unit storing therein data on circuits, each of the circuits having a clock system portion;

a combining unit reading out and combining into a combined circuit the data on circuits stored in said storage unit;

a clock system analyzer analyzing clock system portions of the combined circuit by differentiating clock systems in said combined circuit; and

an analysis result display unit displaying a result of the analysis of the combined circuit with the clock systems of the combined circuit differentiated from each other.

9. A computer-aided logic circuit designing apparatus according to claim 8 further comprising:

a correcting unit correcting said data on circuits based on the result of analysis displayed by said analysis result display unit.

10. A computer-aided logic circuit designing apparatus according to claim 8, wherein said clock system analyzer extracts an asynchronous circuit portion from said combined circuit through analysis of a clock system, and said analysis result display unit generates, when displaying said result of analysis, an alarm concerning the asynchronous circuit portion extracted by said clock system analyzer.

11. A computer-aided logic circuit designing apparatus according to claim 8, wherein said clock system analyzer obtains said analysis result in which data for types of clock system, data on clock input elements, and data for warning of troubles in clock systems are correlated to each other.

12. A computer-aided logic circuit designing apparatus designing a logic circuit by integrating data on circuits comprising:

a storage unit storing therein data on circuits, each of the circuits having one or more clock input elements, each of the clock input elements constituting a clock system portion;

a combining unit reading out and combining into a combined circuit the data on circuits stored in said storage unit;

a clock system analyzer analyzing clock system portions of the combined circuit by differentiating clock systems in said combined circuit; and

an analysis result display unit displaying a result of the analysis of the combined circuit with the clock systems of the combined circuit differentiated from each other.

13. A computer-aided logic circuit designing apparatus according to claim 12 further comprising:

a correcting unit correcting said data on circuits based on the result of analysis displayed by said analysis result display unit.

14. A computer-aided logic circuit designing apparatus according to claim 12, wherein said clock system analyzer extracts an asynchronous circuit portion from said combined circuit through analysis of a clock system, and said analysis result display unit generates, when displaying said result of analysis, an alarm concerning the asynchronous circuit portion extracted by said clock system analyzer.

15. A computer-aided logic circuit designing apparatus according to claim 12, wherein said clock system analyzer obtains said analysis result in which data for types of clock system, data on clock input elements, and data for warning of troubles in clock systems are correlated to each other.

16. A computer-aided logic circuit designing method of designing a logic circuit by integrating data on circuits comprising:

combining data on circuits into a combined circuit, each of the circuits having a clock system portion;

analyzing clock system portions of the combined circuit by differentiating clock systems in said combined circuit; and

displaying the result of analysis of the combined circuit with the clock systems of the combined circuit differentiated from each other.

17. A computer-aided logic circuit designing method of designing a logic circuit by integrating data on circuits comprising:

combining data on circuits into a combined circuit, each of the circuits having one or more clock input elements, each of the clock input elements constituting a clock system portion;

analyzing clock system portions of the combined circuit by differentiating clock systems in said combined circuit; and

displaying the result of analysis of the combined circuit with the clock systems of the combined circuit differentiated from each other.

18. A clock system analyzer for a computer-aided circuit designing apparatus designing a circuit by combining data on circuits into a combined circuit, each of the circuits having a clock system portion, the clock system analyzer comprising:

a clock system analyzer unit to analyze clock system portions of the combined circuit by differentiating clock systems in said combined circuit; and

an analysis result display unit displaying an analysis result of the combined circuit with the clock systems of the combined circuit differentiated from each other.