Semiconductor integrated circuit and method of designing the same

• US 6,216,256 B1
• Filed: 05/20/1998
• Issued: 04/10/2001
• Est. Priority Date: 05/22/1997
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Nagahara, Izuru, Inoue, Koji, Sawada, Hirokazu
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Speight, Jibreel
• Application Number:
  US09/081,621
• Time in Patent Office: 1,056 Days
• Field of Search: 716/6, 324/763, 326/46, 327/277, 368/117, 365/233
• US Class Current: 716/114
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/3312 Timing analysis

Abstract

The layout of a semiconductor IC is determined making use of a first logical cell of an ordinary flip-flop based on a logical net. Logical simulation is performed according to the result of the layout, that is, the layout information. The possibility of erroneous operation caused by timing deviations is verified by comparing the timing information from the result of the logical simulation with the design specifications. Furthermore, the logical cells at points where there is the possibility of erroneous operation caused by timing deviations are replaced by second or third logical cells having delay elements connected to data input or output terminals of the flip-flops. The final layout of the semiconductor IC is then decided.

Claims

1. A method of design of a semiconductor IC comprising:

a first step of providing, as selectable logical cells, a first logical cell comprising a flip-flop, a second logical cell comprising a flip-flop having the same characteristic as that of the flip-flop of the first logical cell and a delay element connected to a signal input terminal of that flip-flop, and a third logical cell comprising a flip-flop having the same characteristic as that of the flip-flop of the first logical cell and a delay element connected to a signal output terminal of that flip-flop,

a second step of determining layout and interconnections in the semiconductor IC based on a given logical net without using the second and third logical cells and outputting layout information,

a third step of performing logical simulation based on the layout information to obtain timing information,

a fourth step of verifying the possibility of erroneous operation due to timing deviations by comparing the timing information with given design specifications, and

a fifth step of determining layout and interconnections in the semiconductor IC by replacing a first logical cell with a second or third logical cell at a location determined to have a possibility of erroneous operation caused by timing deviations as a result of verification of the fourth step and outputting the layout information,

wherein the fourth step determines there is a possibility of erroneous operation due to timing deviations for cascade-connected flip-flops controlled in timing by the same clock when the signal propagation delay for a clock signal path between any two first and second flip-flops connected in the cascade-connected flip-flops is greater than the sum of the signal propagation delay of the first flip-flop, the signal propagation delay of the signal path between the first flip-flop and the second flip-flop, and the difference between the setup time and the holding time of the second flip-flop, and

wherein the fifth step replaces the first logical cell having the first flip-flop by the third logical cell or replaces the first logical cell having the second flip-flop by the second logical cell when it determines there is a possibility of erroneous operation caused by timing deviations as a result of the verification of the fourth step.