FPGA device and method that includes a variable grain function architecture for implementing configuration logic blocks and a complimentary variable length interconnect architecture for providing configurable routing between configuration logic blocks

• US 6,216,257 B1
• Filed: 06/26/2000
• Issued: 04/10/2001
• Est. Priority Date: 10/09/1997
• Status: Expired due to Term

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Vantiss (Lattice Semiconductor Corporation)
• Inventors: Agrawal, Om P., Nguyen, Bai, Sharpe-Geisler, Bradley A., Chang, Herman M., Tran, Giap H.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Speight, Jibreel
• Application Number:
  US09/603,807
• Time in Patent Office: 288 Days
• Field of Search: 326/39, 326/41, 716/12, 716/16, 716/17
• US Class Current: 326/41
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17756 for partial configuration or partial reconfiguration
• CPC Class Codes: H03K 19/17758 for speeding up configuration or reconfiguration
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

A field-programmable gate array device (FPGA) having plural rows and columns of logic function units is organized with symmetrical and complementary Variable Grain Architecture (VGA) and Variable Length Interconnect Architecture (VLI). Synthesis mapping exploits the diversified and symmetric resources of the VGA and VLI to efficiently pack function development into logic units of matched granularity and to transfer signals between logic units with interconnect lines of minimal length.

Claims

1. A method for configuring an FPGA device having plural variable grain blocks (VGB'"'"'s) each including wedged-together, fine grained, function-imrDlementingq constructs and overlapping coarse grained, function-implementing constructs, and the FPGA device further having diversified VGB interconnect resources, wherein said diversified VGB interconnect resources include:

non-global, maximum length lines;

short-haul, general interconnect lines that sean a distance of at least two VGB'"'"'s; and

intermediate length lines that are shorter than the non-global, maximum length lines but lonaer than said short-haul, general interconnect lines and the FPGA device further having for each VGB local feedback lines which are each dedicated to providing intraconnect within the respective VGB;

said configuring method comprising;

(a) mapping synthesis definitions to fit within the fine or coarse arained constructs of the variable grain blocks (VGB'"'"'s) of the FPGA device; and

(b) rearranging the mapped constructs to increase nucleated function development within the VGB'"'"'s, as opposed to maximizing cascaded function development through use of multiple ones of the VGB'"'"'s and use of said intermediate lenath lines or maximum length lines for the same function development, said increase of nucleated function development operating to reduce utilization of said VGB interconnect due to cascaded development of functions through multiple VGB'"'"'s.

2. The FPGA configuring method of claim 1 wherein said rearranging of the mapped constructs comprises:

(b.1) finding cascaded function developments; and

(b.2) changing said cascaded function developments into nucleated function developments to an extent allowed by the coarse grained, function-implementing constructs of the VGB'"'"'s.

3. The FPGA configuring method of claim 2 wherein each VGB includes a plurality of Configurable Building Blocks (CBB'"'"'s) each having programmably-configurable, function developing resources that can be programmably folded-together to provide coarser function development, and wherein said rearranging of the mapped constructs further comprises:

(b.3) maximizing folded-together utilization of the function developing resources within a given one or more of said CBB'"'"'s.

4. The FPGA configuring method of claim 2 wherein each VGB includes programmably-configurable, function developing resources that can be programmably folded-together to provide coarser function development, and wherein said rearranging of the mapped constructs further comprises:

(b.3) maximizing folded-together utilization of the function developing resources within a given one or more of said VGB'"'"'s.

5. The FPGA configuring method of claim 4 wherein adjacent ones of said VGB'"'"'s can be programmably folded-together to provide yet coarser function development, and wherein said rearranging of the mapped constructs further comprises:

(b.3) maximizing folded-together utilization of the function developing resources of adjacent ones of said VGB'"'"'s by programmably folding-together said adjacent VGB'"'"'s.

6. The FPGA configuring method of claim 5 wherein said, foldable-together, adjacent ones of the VGB'"'"'s are wedged together so as not have intervening interconnect channels passing therebetween.

7. The FPGA configuring method of claim 1 wherein said diversified VGB interconnect resources further include a plurality of programmable switchboxes having resources for providing programmably-configurable interconnection between respective ones of said short-haul, general interconnect lines and intermediate length lines, and wherein said configuring method further comprises:

(c) placing signal-sharing ones of the mapped constructs in adjacent VGB'"'"'s so as to reduce, in subsequent inter-VGB signal routing usage of the switchbox resources for said function developments of increased nucleation.

8. The FPGA configuring method of claim 1 wherein said diversified VGB interconnect resources further include a plurality of programmable switchboxes having resources for providing programmably-configurable interconnection between respective ones of said short-haul, general interconnect lines and intermediate length lines, wherein said diversified VGB interconnect resources further include direct connect lines (DCL'"'"'s) that each provide dedicated interconnection between a respective, signal sourcing VGB a plurality of other VGB'"'"'s, said DCL'"'"'s not needing switchboxes to provide their respective, dedicated interconnections, and wherein said configuring method further comprises:

(c) placing signal-sharing ones of the mapped constructs in directly-connected ones of said VGB'"'"'s so as to reduce, in subsequent inter-VGB signal routing usage of the switchbox resources for said function developments of increased nucleation.

9. A method for configuring an FPGA having plural variable grain blocks (VGB'"'"'s) each including granulatable, coarse function-implementing constructs that can be programmably granulated into non-overlapping finer grained, function-implementing constructs, and the FPGA further having diversified VGB interconnect resources, wherein said diversified VGB interconnect resources include:

short-haul, general interconnect lines that span a distance of at least two VGB'"'"'s but less than that of a row of VGB'"'"'s; and

intermediate length lines that are shorter than said row of VGB'"'"'s but longer than said short-haul, general interconnect lines, and the FPGA further having for each VGB local feedback lines which are each dedicated to providing intraconnect within the respective VGB and between said coarse and finer grained, function-implementing constructs of the VGB;

said configuring method comprising;

(a) mapping synthesis definitions to fit within the fine and coarse grained constructs of the variable grain blocks (VGB'"'"'s) of the FPGA device; and

(b) congregating the mapped constructs to increase nucleated function development within the VGB'"'"'s, said increase of nucleated function development operating to reduce utilization of said VGB interconnect resources due to cascaded development of functions through multiple VGB'"'"'s.

10. A reconfigurable FPGA provided in an integrated circuit and comprising:

(a) a plurality of variable grain blocks (VGB'"'"'s) each including fine grained, function-implementing constructs and overlapping coarse grained, function-implementing constructs;

(b) diversified VGB interconnect resources, wherein said diversified VGB interconnect resources include;

(b.

     1) non-global, maximum length interconnect lines;

(b.2) short-haul, general interconnect lines that span a distance of at least two VGB'"'"'s; and

(b.3) intermediate length interconnect lines that are shorter than the non-global, maximum length interconnect lines but longer than said short-haul, general interconnect lines;

(c) a plurality of tristateable line drivers coupled to drive respective ones of said interconnect lines, each tristateable line driver having an output enable terminal for selectively enabling the driver to drive a respective one of said interconnect lines,

(c.1) where plural ones of said interconnect lines can each be driven by multiple ones of said tristateable line drivers; and

(d) an output enable allocator operatively coupled to the respective output enable terminals of the multiple tristateable line drivers of a given one or more of said plural interconnect lines for selecting as a line master, one of the multiple tristateable line drivers of each of the given one or more of said plural interconnect lines.