Apparatus and method for processing data with an arithmetic unit

• US 6,217,234 B1
• Filed: 06/07/1995
• Issued: 04/17/2001
• Est. Priority Date: 07/29/1994
• Status: Expired due to Term

• Current Assignee: Talon Research LLC
• Original Assignee: Discovision Associates (Pioneer Corporation)
• Inventors: Jones, Anthony Mark, Barnes, David Andrew, Sotheran, Martin William, Dewar, Kevin D.
• Primary Examiner(s): Ramirez, Ellis B.
• Application Number:
  US08/487,356
• Time in Patent Office: 2,141 Days
• Field of Search: 364/514.R, 370/60, 370/94.2, 370/94.1, 455/4.2, 395/800
• US Class Current: 709/247
• CPC Class Codes: G06F 12/0207 with multidimensional access, e.g. row/column, matrix
• CPC Class Codes: G06F 12/04 Addressing variable-length words or parts of words
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: H04N 19/13 Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 19/91 Entropy coding, e.g. variable length coding [VLC] or arithmetic coding
• CPC Class Codes: H04N 21/4305 Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/43072 of multiple content streams on the same device
• CPC Class Codes: H04N 21/44004 involving video buffer management, e.g. video decoder buffer or video display buffer

Abstract

An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system, including memory addressing, transforming data using a common processing block, time synchronization, asynchronous swing buffering, storing of video information, a parallel Huffman decoder, and the like.

Claims

1. A system for transforming digital signals in which the digital signals are arranged in groups of N data input words, comprising:

a pre-common processing circuit (PREC) arranged to perform predetermined pairing operations on odd-numbered ones of the input words and to transmit even-numbered ones of the input words to pre-common outputs;

a common processing circuit (CBLK) receiving both odd-numbered and even-numbered data from said pre-common processing circuit (PREC) for forming odd and even common processing output values respectively; and

a post-common processing circuit (POSTC) arranged to perform predetermined output scaling operations on the odd common processing output values to form post-processed odd values and to arithmetically combine the post-processed odd values with the even common processing output values to generate high- and low-order output words, the system being arranged such that the output words contain transformation values corresponding to the input data words, wherein said post-common processing circuit comprises;

a first latch defining a first data stream source and a second latch defining a second data stream source;

said first and said second latches being in communication with an arithmetic unit;

said arithmetic unit communicating data to a transposer;

said transposer transposing and communicating said data to said second latch;

said second latch being arranged to absorb data; and

said second latch and said first latch communicating said first and second data streams in an interleaved manner to said arithmetic unit, further defined that in said communication in the interleaved manner said second latch does not interrupt communication from said first latch;

whereby a common arithmetic unit is used for said first and said second data streams.

2. The system according to claim 1 wherein said second latch comprises a series of interconnected latches to form a buffer, said buffer being configurable in size to accommodate variable rates of data reception and transmission.

3. The system according to claim 1, wherein said second latch communicates said second data stream to said arithmetic unit only when said second latch is filled with a predetermined amount of data.

4. A system for transforming digital signals from a frequency to a time domain in which the digital signals are arranged in groups of N data input words, comprising:

a pre-common processing circuit (PREC) arranged to perform predetermined pairing operations on odd-numbered ones of the input words and to transmit even-numbered ones of the input words to pre-common outputs;

a common processing circuit (CBLK) receiving both odd-numbered and even-numbered data from said pre-common processing circuit (PREC) for forming odd and even common processing output values respectively; and

a post-common processing circuit (POSTC) arranged to perform predetermined output scaling operations on the odd common processing output values to form post-processed odd values and to arithmetically combine the post-processed odd values with the even common processing output values to generate high- and low-order output words, the system being arranged such that the output words contain transformation values corresponding to the input data words, the system being arranged such that the output words contain inverse discrete cosine transformation values corresponding to the input data words, wherein said post-common processing circuit comprises;

a first latch defining a first data stream source and a second latch defining a second data stream source;

said first and said second latches being in communication with an arithmetic unit;

said arithmetic unit communicating data to a transposer;

said transposer transposing and communicating said data to said second latch;

said second latch being arranged to absorb data; and

said second latch and said first latch communicating said first and second data streams in an interleaved manner to said arithmetic unit, further defined that in said communication in the interleaved manner said second latch does not interrupt communication from said first latch;

whereby a common arithmetic unit is used for said first and said second data streams.

5. The system according to claim 4, wherein said second latch comprises a series of interconnected latches to form a buffer, said buffer being configurable in size to accommodate variable rates of data reception and transmission.

6. The system according to claim 5, wherein said second latch communicates said second data stream to said arithmetic unit only when said second latch is filled with a predetermined amount of data.