Integrated circuit package for flip chip and method of forming same

• US 6,218,214 B1
• Filed: 10/21/1999
• Issued: 04/17/2001
• Est. Priority Date: 04/13/1998
• Status: Expired due to Term

• Current Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Newton, Charles M., Panchou, Karen A.
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): LATTIN, CHRISTOPHER W
• Application Number:
  US09/422,011
• Time in Patent Office: 544 Days
• Field of Search: 438/106, 438/107, 438/108, 438/118, 438/119, 438/125
• US Class Current: 438/108
• CPC Class Codes: H01L 22/00 Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/2612 Auxiliary members for layer connectors, e.g. spacers
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

An integrated circuit package includes a ceramic substrate having a cut out configured to receive a flip chip. The cut out includes vias formed as through holes. A flip chip is received within the cut out of the ceramic substrate and has conductive bumps formed thereon corresponding to the electrical input/output contacts of the flip chip. The conductive bumps are received within the through holes of the ceramic substrate. A second integrated circuit chip is mounted on the flip chip in back-to-back relationship. A controlled impedance line is secured to the conductive bumps and acts as a coax. In another aspect of the present invention, a heat sink can be mounted on the back of the flip chip, and the second integrated circuit chip mounted on the heat sink.

Claims

1. A method of forming an integrated circuit package comprising:

forming a ceramic substrate having a cut out configured to receive a flip chip, the cutout including through holes;

forming conductive bumps onto a flip chip that correspond to the electrical input/output contacts of the flip chip;

receiving the flip chip within the cut out of the ceramic substrate so that the conductive bumps are received within the through holes of the ceramic substrate; and

securing a controlled impedance line to the conductive bumps.

2. A method according to claim 1, and further comprising the steps of screen printing the conductive bumps onto the flip chip.

3. A method according to claim 2, and further comprising the steps of forming the conductive bumps from gold ball bumps.

4. A method according to claim 1, and further comprising the steps of plating the through holes with a conductive ink.

5. A method according to claim 1, and further comprising the steps of securing a controlled impedance line to the conductive bumps by applying an epoxy bond.

6. A method according to claim 1, and further comprising the step of mounting a second integrated circuit chip back-to-back on the flip chip received within the cut out.

7. A method according to claim 6, and further comprising the step of grounding together the back-to-back flip chip and second integrated circuit chip.

8. A method according to claim 6, and further comprising the step of wire bonding the second integrated circuit chip to conductive patterns formed on the ceramic substrate.

9. A method according to claim 6, and further comprising the step of forming a stepped cut within the ceramic substrate out to receive the flip chip and the second integrated circuit chip.

10. A method according to claim 1, and further comprising the step of forming the ceramic substrate from green tape ceramic.

11. A method according to claim 1, and further comprising the step of forming the conductive bumps as soldered conductive bumps.

12. A method according to claim 1, and further comprising forming the conductive bumps as epoxy bumps impregnated with conductive material.

13. A method of forming an integrated circuit package comprising:

forming a ceramic substrate having a cut out configured to receive a flip chip, wherein the cut out includes through holes;

forming conductive bumps onto a flip chip corresponding to the electrical input/output contacts of the flip chip;

receiving the flip chip within the cut out of the ceramic substrate so that the conductive bumps are received within the through holes;

mounting a second integrated circuit chip on the flip chip in back-to-back relationship; and

grounding together the flip chip and second integrated circuit chip.

14. A method according to claim 13, and further comprising the step of wire bonding the second integrated circuit chip to conductive patterns formed on the ceramic substrate.

15. A method according to claim 13, and further comprising the steps of forming the conductive bumps as gold ball bumps.

16. A method according to claim 13, and further comprising the steps of forming the conductive bumps as epoxy bumps impregnated with conductive material.

17. A method according to claim 13, and further comprising the step of adding a heat sink on top of the flip chip, followed by adding the second integrated circuit chip.

18. A method according to claim 13, and further comprising the steps of screen printing the conductive bumps onto the flip chip die.

19. A method according to claim 13, and further comprising the steps of plating the through holes with a conductive ink.

20. A method according to claim 13, and further comprising the steps of securing a controlled impedance line to the conductive bumps.

21. A method according to claim 13, and further comprising the step of forming the ceramic substrate from green tape ceramic.

22. A method according to claim 13, and further comprising the step of forming a stepped cut out within the ceramic substrate to receive the flip chip and the second integrated circuit chip.

23. A method according to claim 13, and further comprising the step of securing the second integrated circuit chip to the flip chip by an adhesive bond.

24. A method of forming an integrated circuit package comprising:

forming a ceramic substrate having a cut out configured to receive a flip chip, wherein the cut out includes through holes;

forming conductive bumps onto a flip chip corresponding to the electrical input/output contacts of the flip chip;

receiving the flip chip within the cut out of the ceramic substrate so that the conductive bumps are received within the through holes;

mounting a heat sink on the flip chip;

mounting a second integrated circuit chip on the heat sink; and

wire bonding the second integrated circuit chip to conductive patterns formed on the ceramic substrate.

25. A method according to claim 24, and further comprising the steps of securing the heat sink to the flip chip by a conductive adhesive.

26. A method according to claim 24, and further comprising the steps of securing the second flip chip by an adhesive.

27. A method according to claim 24, and further comprising the steps of screen printing conductive patterns on the ceramic substrate, and of wire bonding the second integrated circuit chip to conductive patterns formed on the ceramic substrate.

28. A method according to claim 24, and further comprising the steps of forming the conductive bumps by soldering.

29. A method according to claim 24, and further comprising the steps of screen printing conductive bumps on the flip chip.

30. A method according to claim 29, and further comprising the steps of forming the conductive bumps from gold ball bumps.

31. A method according to claim 24, and further comprising the steps of plating the through holes with a conductive ink.

32. A method according to claim 24, and further comprising the steps of securing a controlled impedance line to the conductive bumps.

33. A method according to claim 24, and further comprising the step of grounding together the flip chip and second integrated circuit chip.

34. A method according to claim 24, and further comprising the step of wire bonding the second integrated circuit chip mounted to conductive portions formed on the ceramic substrate.

35. A method according to claim 24, and further comprising the step of forming the ceramic substrate from green tape ceramic.

36. A method according to claim 24, and further comprising the step of forming a stepped cut out within the ceramic substrate to receive the flip chip and the second integrated circuit chip.