Semiconductor device having high breakdown voltage and method of manufacturing the same

• US 6,218,217 B1
• Filed: 07/18/2000
• Issued: 04/17/2001
• Est. Priority Date: 04/11/1996
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Nakamura, Katsumi, Uenishi, Akio
• Primary Examiner(s): Lee, Eddie C.
• Assistant Examiner(s): Brock, II, Paul E
• Application Number:
  US09/618,761
• Time in Patent Office: 273 Days
• Field of Search: 438/134, 438/270, 438/271, 438/588, 438/587, 438/212, 438/259, 438/589, 438/133, 438/135, 438/138, 257/334, 257/141, 257/332, 257/139, 257/138, 257/341, 257/329, 257/331, 257/152, 257/330
• US Class Current: 438/138
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

In a semiconductor device with a high breakdown voltage, insulating layers are buried at regions in n⁻ silicon substrate located between gate trenches which are arranged with a predetermined pitch. This structure increases a carrier density at a portion near an emitter, and improves characteristic of an IGBT of a gate trench type having a high breakdown voltage.

Claims

1. A method of manufacturing a semiconductor device with a high breakdown voltage comprising the steps of:

forming a first semiconductor substrate of a first conductivity type provided at its main surface with an insulating layer;

arranging a second semiconductor substrate of the first conductivity type over said insulating layer to form a semiconductor substrate having first and second main surfaces and including said insulating layer interposed therebetween;

forming a first impurity layer of a second conductivity type at said first main surface of said semiconductor substrate;

forming an impurity region of the first conductivity type at a predetermined region of a surface of said first impurity layer;

forming a second impurity layer of the second conductivity type at said second main surface;

forming a groove extending to said insulating layer at said impurity region;

removing the insulating layer exposed at said groove;

forming an epitaxial growth layer having the same impurity concentration as said semiconductor substrate at an inner surface of said groove by an epitaxial growth method;

forming a gate insulating film at a surface of said epitaxial growth layer in said groove;

filling said groove with an electric conductor to form a gate electrode;

covering a portion of said gate electrode exposed at said first main surface with an insulating film;

forming a first main electrode layer covering said first main surface and electrically connected to said first impurity layer and said impurity region; and

forming a second main electrode layer at said second main surface.

2. The method of manufacturing the semiconductor device with a high breakdown voltage according to claim 1, wherein

a thickness of said insulating layer is equal to or smaller than a quadruple of a thickness of said gate insulating film.

3. The method of manufacturing the semiconductor device with a high breakdown voltage according to claim 1, further comprising the step of forming a third impurity layer of the first conductivity type having an impurity concentration higher than that of said semiconductor substrate and located at a portion of said second impurity layer near said semiconductor substrate.

4. A method of manufacturing a semiconductor device with a high breakdown voltage comprising the steps of:

forming a first semiconductor substrate of a first conductivity type provided at its main surface with insulating layers with a predetermined pitch;

forming a second semiconductor substrate of the first conductivity type provided at its main surface with concavities of the same width and thickness as said insulating layer with the same pitch as said insulating layers;

laminating the main surfaces of said first and second semiconductor substrates together to form a semiconductor substrate having first and second main surfaces and including said insulating layers interposed therebetween with a predetermined pitch;

forming a first impurity layer of a second conductivity type at the first main surface of said semiconductor substrate;

forming an impurity region of the first conductivity type at a predetermined region of the surface of said first impurity layer;

forming a second impurity layer of the second conductivity type at said second main surface;

forming a groove extending to said semiconductor substrate through a region between said insulating layers at said impurity region;

forming a gate insulating film at an inner surface of said groove;

filling said groove with an electric conductor to form a gate electrode;

covering a portion of said gate electrode exposed at said first main surface with an insulating film;

forming a first main electrode layer electrically connected to said first impurity layer and said impurity region and covering said first main surface; and

forming a second main electrode layer at said second main surface.

5. The method of manufacturing the semiconductor device with a high breakdown voltage according to claim 4, wherein

a thickness of said insulating layer is equal to or smaller than a quadruple of a thickness of said gate insulating film.

6. The method of manufacturing the semiconductor device with a high breakdown voltage according to claim 4, further comprising the step of forming a third impurity layer of the first conductivity type having an impurity concentration higher than that of said semiconductor substrate and located at a portion of said second impurity layer near said semiconductor substrate.

7. The method of manufacturing the semiconductor device with a high breakdown voltage according to claim 4, wherein

a bottom of said groove is located at a position deeper than said insulating layer in said step of forming said groove.

8. A method of manufacturing a semiconductor device with a high breakdown voltage comprising the steps of:

preparing a semiconductor substrate of a first conductivity type having first and second main surfaces;

forming a first impurity layer of a second conductivity type at a predetermined region of said first main surface of said semiconductor substrate;

forming an impurity region of the second conductivity type at a predetermined region of a surface of said first impurity layer;

forming a second impurity layer of the second conductivity type at said second main surface;

forming a first groove extending to said semiconductor substrate at said impurity region;

forming a plurality of second grooves at said semiconductor substrate defined by said impurity region;

forming insulating films at inner surfaces of said first and second grooves;

filling said first and second grooves with electric conductors fill to form a buried gate electrode and a buried emitter electrode, respectively;

covering portions of said buried gate electrode and said buried emitter electrode exposed at said first main surface with a second insulating film;

forming a contact hole extending to said buried emitter electrode at said second insulating film formed on said buried emitter electrode;

forming a first main electrode layer covering said first main surface and electrically connected to said first impurity layer, said impurity region and said buried emitter electrode; and

forming a second main electrode layer at said second main surface.

9. The method of manufacturing the semiconductor device with a high breakdown voltage according to claim 8, further comprising the step of forming a third impurity layer of the first conductivity type having an impurity concentration higher than that of said semiconductor substrate and located at a portion of said second impurity layer near said semiconductor substrate.

10. The method of manufacturing the semiconductor device with a high breakdown voltage according to claim 8, further comprising the step of forming a first impurity layer of the second conductivity type formed at a predetermined region of said first main surface of said semiconductor substrate extending from said first main surface into said semiconductor substrate in a depthwise direction.

11. The method of manufacturing the semiconductor device with a high breakdown voltage according to claim 8, wherein

the step of forming said second groove further comprising the step of forming a plurality of said second grooves at said semiconductor substrate sandwiched by said impurity regions.