Semiconductor device and method for fabricating the same

• US 6,218,248 B1
• Filed: 04/02/1999
• Issued: 04/17/2001
• Est. Priority Date: 04/02/1998
• Status: Expired due to Term

• Current Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Original Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Inventors: Son, Jeong Hwan, Hwang, Jeong Mo
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): PHAM, HOAI V
• Application Number:
  US09/285,258
• Time in Patent Office: 746 Days
• Field of Search: 257/349, 257/347, 438/412, 438/404, 438/405, 438/280, 438/294, 438/304, 438/295
• US Class Current: 438/294
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0218 of field effect structures
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device and a method for fabricating the same are disclosed, in which floating body effect is reduced by applying a bias to a body in an SOI MOSFET. The semiconductor device includes first and second impurity ion implanting layers of a conductivity type formed in a semiconductor substrate having a buried oxide film and surface silicon layers thereon, first and second transistors of a conductivity type respectively formed on the first and second impurity ion implanting layers, having source/drain regions and a gate, trenches formed between the first and second transistors, single crystal silicon layers connected to any one of the source/drain regions of the respective transistors and the first and second impurity ion implanting layers at sides of the trenches, and carrier exhausting electrodes connected to the first and second impurity ion implanting layers at one sides of the respective transistors, for exhausting carrier generated by ionization impact in the respective transistors.

Claims

1. A method for fabricating a semiconductor device comprising:

forming first and second transistors of a type defined by impurity ion implanting layers within a semiconductor substrate having a buried oxide film and surface silicon layers thereon, the first and second transistors having source/drain regions, a gate and single crystal silicon layers connected to the first and second impurity ion implanting layers;

implanting an impurity ion into at least one of the source/drain regions of the respective transistors, and into the single crystal silicon layers connected to the first and second impurity ion implanting layers; and

forming carrier exhausting electrodes, each connected to one of the impurity ion implanting layers at one side of each of the first and second transistors, where the carrier exhausting electrodes exhaust carriers generated by ionization impact in the respective transistors.

2. A method for fabricating a semiconductor device comprising:

forming first and second transistors of a type defined by impurity ion implanting layers within a semiconductor substrate having a buried oxide film and surface silicon layers thereon, the first and second transistors having source/drain regions and a gate;

forming trenches between the first and second transistors;

forming single crystal silicon layers at sides of the trenches, each single crystal silicon layer being connected to any one of the source/drain regions of the respective transistors and the first and second impurity ion implanting layers; and

forming carrier exhausting electrodes, each connected to one of the impurity ion implanting layers at one side, of each of the first and second transistors, wherein the carrier exhausting electrodes exhaust carriers generated by ionization impact in the respective transistors.

3. The method claimed in claim 2, wherein the single crystal silicon layers are formed at sides of the trenches in a sidewall form.

4. The method claimed in claim 2, wherein the trenches are formed up to a certain depth in the body of the semiconductor substrate below the buried oxide film.

5. A method for fabricating a semiconductor device comprising:

sequentially forming a pad oxide film and a nitride film on a semiconductor substrate having a buried oxide film and surface silicon layers thereon;

selectively etching the pad oxide film and the nitride film to form trenches;

forming undoped polysilicon sidewalls at sides of the trenches;

thermally oxidizing outer sides of the undoped polysilicon sidewalls to form a first dielectric layer;

recrystallizing inner sides of the undoped polysilicon sidewalls using the silicon layers and a body of the semiconductor substrate as seeds to form single crystal silicon layers;

depositing an oxide film on an entire surface including the trenches and planarizing the oxide film to form a second dielectric layer;

selectively removing the nitride film and the pad oxide film;

forming a first photoresist over a portion of the semiconductor device where a PMOS transistor will be formed;

implanting an impurity ion into a channel region of the surface silicon layers and single crystal silicon layer at a first side of the trenches and within the body of the semiconductor substrate using the first photoresist as a mask;

forming a gate oxide film and a gate electrode on the channel region into which the impurity ion is implanted;

selectively implanting the impurity ion into the gate oxide film and the gate electrode to form source/drain regions; and

forming carrier exhausting electrodes on the surface silicon layers at a second of the trenches opposing the first side.

6. The method claimed in claim 5, wherein the buried oxide film has a thickness of 1000˜

4000 Å and

the surface silicon layer has a thickness of 300˜

2000 Å

.

7. The method claimed in claim 5, wherein the semiconductor substrate is formed by at least one of a SIMOX, BESOI and Smart-cut method.

8. The method claimed in claim 5, wherein the pad oxide film is formed at a thickness of 100˜

500 Å

by thermal oxidation or CVD process.

9. The method claimed in claim 5, wherein the nitride film is deposited at a thickness of 500˜

2000 Å

by CVD process.

10. The method claimed in claim 5, wherein the trenches are formed by etching the semiconductor substrate below the buried oxide film at a depth of 300˜

1000 Å

.

11. The method claimed in claim 5, wherein the undoped polysilicon sidewalls are formed by depositing the undoped polysilicon on the entire surface of the nitride film including the trenches at a thickness of 500˜

1500 Å and

then etching the deposited undoped polysilicon from areas other than sides of the trenches.

12. The method claimed in claim 5, wherein the sidewalls are recrystallized such that the first dielectric layer has a thickness of 50˜

200 Å and

the single crystal silicon layer has a thickness of 100˜

300 Å

.

13. The method claimed in claim 5, wherein the oxide film is deposited by a CVD or HDP process and planarized by CMP process to form the second dielectric layer.