Method of fabricating a self-aligned bipolar junction transistor in silicon carbide and resulting devices

• US 6,218,254 B1
• Filed: 09/22/1999
• Issued: 04/17/2001
• Est. Priority Date: 09/22/1999
• Status: Expired due to Term

• Current Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Original Assignee: Cree Research, Inc. (Wolfspeed, Inc.)
• Inventors: Agarwal, Anant K., Singh, Ranbir, Ryu, Sei-Hyung
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): LATTIN, CHRISTOPHER W
• Application Number:
  US09/401,602
• Time in Patent Office: 573 Days
• Field of Search: 438/309, 438/320, 438/337, 438/341, 438/342, 438/359, 438/364, 438/366, 438/369, 438/931
• US Class Current: 438/364
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66234 Bipolar junction transistors [BJT]
• CPC Class Codes: H01L 29/732 Vertical transistors

Abstract

A method of fabricating a self-aligned bipolar junction transistor in a semiconductor structure having a first layer of silicon carbide generally having a first conductivity type and a second layer of silicon carbide generally having a second conductivity type, opposite to the first conductivity type. The method comprises forming a pillar in the second silicon carbide layer, the pillar having a side wall and defining an adjacent horizontal surface on the second layer, forming a dielectric layer having a predetermined thickness on the second semiconductor layer, including the side wall and the horizontal surface. After formation of the dielectric layer, the dielectric layer on a portion of the horizontal surface adjacent the side wall is anisotropically etched while at least a portion of the dielectric layer remains on the side wall, thereby exposing a portion of the horizontal surface. A portion of the second layer below the exposed portion of the horizontal surface is then doped with a dopant of the first conductivity type to create a doped well region in the second layer which is spaced from the side wall by a distance defined by the thickness of the dielectric layer. Resulting devices are likewise disclosed.

Claims

1. A method of fabricating a self-aligned bipolar junction transistor in a semiconductor structure having a first layer of silicon carbide and a second layer of silicon carbide, the method comprising:

forming a trench in the second silicon carbide layer, the trench having a bottom wall and opposing side walls;

conformally depositing a spacer layer having a predetermined thickness on the second semiconductor layer, including the bottom wall and side walls of the trench;

anisotropically etching the spacer layer from a portion of the bottom wall of the trench between the side walls, thereby exposing a portion of the bottom wall of the trench while at least a portion of the spacer layer remains on the side walls;

doping a region below the exposed portion of the bottom wall with a dopant to create a doped well region below the bottom wall; and

removing the spacer layer.

2. The method of claim 1, wherein the second layer comprises a base region, the well region comprises an emitter region, and the first layer comprises a collector region of the bipolar junction transistor.

3. The method of claim 1, wherein the second layer comprises an emitter region, the well region comprises a base region, and the first layer comprises a collector region of the bipolar junction transistor.

4. The method of claim 1, wherein the step of forming a trench in the second silicon carbide layer comprises etching a portion of the second layer.

5. The method of claim 1, wherein the step of doping a region below the exposed portion of the bottom wall comprises high temperature ion implantation.

6. The method of claim 1, further comprising:

etching a portion of the second layer to form a mesa containing the transistor.

7. The method of claim 6, wherein the step of etching a portion of the second layer is followed by the steps of:

forming a dielectric layer on the mesa, and

anisotropically etching the dielectric layer to reveal contact surfaces.

8. The method of claim 2 or 3, further comprising:

providing ohmic contacts to the base, emitter and collector regions.

9. The method of claim 1, wherein the second layer comprises a layer of heavily doped, p-type silicon carbide.

10. A method of fabricating a self-aligned bipolar junction transistor in a semiconductor structure having a first layer of silicon carbide of a first conductivity type and a second layer of silicon carbide of a second conductivity type, opposite to the first conductivity type and epitaxially deposited on the first layer, the method comprising:

etching the second layer of silicon carbide to form at least one pillar having a first surface opposite the first silicon carbide layer and opposing side walls, and a horizontal surface adjacent the pillar;

forming a spacer layer having a predetermined thickness on the first surface of the pillar, the opposing side walls and the horizontal surface adjacent the pillar;

anisotropically etching the spacer layer from the horizontal surfaces adjacent the pillar while at least a portion of the spacer layer remains on the side walls of the pillar, thereby exposing the horizontal surface;

doping a portion of the second layer of silicon carbide below the exposed portion of the horizontal surface with a dopant of the first conductivity type to create a doped well region in the second layer of silicon carbide; and

removing the spacer layer.

11. The method of claim 10, wherein the second layer comprises a base region, the well region comprises an emitter region, and the first layer comprises a collector region of the bipolar junction transistor.

12. The method of claim 10, wherein the second layer of silicon carbide comprises an emitter region, the well region comprises a base region, and the first layer of silicon carbide comprises a collector region of the bipolar junction transistor.

13. The method of claim 10, wherein the step of forming a pillar in the second silicon carbide layer of silicon carbide comprises etching a portion of the second layer.

14. The method of claim 10, wherein the step of doping a portion of the first layer of silicon carbide comprises high temperature ion implantation.

15. The method of claim 10, further comprising:

etching a portion of the second layer to form a mesa containing the transistor.

16. The method of claim 15, wherein the step of etching a portion of the second layer of silicon carbide is followed by the steps of:

forming a dielectric layer on the mesa, and

anisotropically etching the dielectric layer to reveal contact surfaces.

17. The method of claim 11 or 12, further comprising:

providing ohmic contacts to the base, emitter and collector regions.

18. The method of claim 10, wherein the second layer of silicon carbide comprises a layer of heavily doped, p-type silicon carbide.

19. A method of fabricating a self-aligned bipolar junction transistor in a semiconductor structure having a first layer of silicon carbide of a first conductivity type, a second layer of silicon carbide of a second conductivity type, opposite to the first conductivity type and epitaxially deposited on the first layer, and a second layer of silicon carbide of the first conductivity type epitaxially deposited on the second layer, the method comprising:

forming a trench in the second silicon carbide layer, the trench having a bottom wall and opposing side walls;

depositing a spacer layer having a predetermined thickness on the second semiconductor layer, including the bottom wall and side walls of the trench;

anisotropically etching the spacer layer from a portion of the bottom wall of the trench between the side walls while at least a portion of the spacer layer remains on the side walls, thereby exposing a portion of the bottom wall of the trench;

doping a portion of the second layer below the exposed portion of the bottom wall with a dopant of the first conductivity type to create a doped well region in the second layer; and

removing the spacer layer.

20. A method of fabricating a self-aligned bipolar junction transistor in a semiconductor structure having a first layer of silicon carbide of a first conductivity type, a second layer of silicon carbide of a second conductivity type, opposite to the first conductivity type and epitaxially deposited on the first layer of silicon carbide of a first conductivity type, and a second layer of silicon carbide of the first conductivity type epitaxially deposited on the second layer of silicon carbide of a second conductivity type, the method comprising:

etching the second layer of silicon carbide of a first conductivity type to form at least one pillar having a top wall and opposing side walls, and a horizontal surface adjacent the pillar;

depositing a spacer layer having a predetermined thickness on structure, including top wall and side walls of the pillar and the horizontal surface adjacent the pillar;

anisotropically etching the spacer layer from the horizontal surfaces adjacent the pillar while at least a portion of the spacer layer remains on the side walls of the pillar, thereby exposing the horizontal surface;

doping a portion of the second layer of silicon carbide of a second conductivity type below the exposed portion of the horizontal surface with a dopant of the first conductivity type to create a doped well region in the second layer; and

removing the spacer layer.