Method for providing a dopant level for polysilicon for flash memory devices
First Claim
1. A method for providing a NAND-type flash memory device, comprising:
- (a) forming a select gate oxide layer in a select transistor area of a substrate and a tunnel oxide layer in a memory cell area of the substrate;
(b) forming a doped amorphous silicon layer on the select gate oxide layer and the tunnel oxide layer, the doped amorphous silicon layer having a dopant level which simultaneously avoids a select transistor word line resistance problem and a charge gain/charge loss problem wherein the doped amorphous silicon layer has a dopant level between approximately 5×
1018 and 8×
1019 ions/cm3 of phosphorus, and wherein the select transistor word line resistance is no greater than approximately 1500 ohms per square;
(c) forming an insulating layer on the doped amorphous silicon layer;
(d) forming a control gate layer on the insulating layer; and
(e) etching at least the doped amorphous silicon layer, the insulating layer, and the control gate layer to form at least one memory cell stack structure and at least one select transistor stack structure.
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Abstract
The present invention provides a method and a NAND-type flash memory device. The method includes forming a select gate oxide layer in a select transistor area of a substrate and a tunnel oxide layer in a memory cell area of the substrate; forming a doped amorphous silicon layer on the select gate oxide layer and the tunnel oxide layer, the doped amorphous silicon layer having a dopant level which simultaneously avoids a select transistor word line high resistance problem and a charge gain/charge loss problem; forming an insulating layer on the doped amorphous silicon layer; forming a control gate layer on the insulating layer; and etching at least the doped amorphous silicon layer, the insulating layer, and the control gate layer to form at least one memory cell stack structure and at least one select transistor stack structure. In a preferred embodiment, the polysilicon layer which forms both the floating gate of the flash memory cell and the select gate of the select transistor of the device is doped with between approximately 5×1018 and 8×1019 ions/cm3 of phosphorus. With this dopant level, the contact resistance of the select transistor'"'"'s control gate is low, thus keeping the word line resistivity of the device low. Simultaneously, contamination of the tunnel oxide of the flash memory cell by the dopant is limited, allowing for the interface between the floating gate and the tunnel oxide to be smooth, which prevents charge gain/loss problems. Thus, the reliability of the device is increased.
70 Citations
30 Claims
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1. A method for providing a NAND-type flash memory device, comprising:
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(a) forming a select gate oxide layer in a select transistor area of a substrate and a tunnel oxide layer in a memory cell area of the substrate;
(b) forming a doped amorphous silicon layer on the select gate oxide layer and the tunnel oxide layer, the doped amorphous silicon layer having a dopant level which simultaneously avoids a select transistor word line resistance problem and a charge gain/charge loss problem wherein the doped amorphous silicon layer has a dopant level between approximately 5×
1018 and 8×
1019 ions/cm3 of phosphorus, and wherein the select transistor word line resistance is no greater than approximately 1500 ohms per square;
(c) forming an insulating layer on the doped amorphous silicon layer;
(d) forming a control gate layer on the insulating layer; and
(e) etching at least the doped amorphous silicon layer, the insulating layer, and the control gate layer to form at least one memory cell stack structure and at least one select transistor stack structure. - View Dependent Claims (2, 3, 4, 5, 6)
(a1) growing a first oxide layer in the select transistor area and the memory cell area;
(a2) removing the first oxide layer in the memory cell area; and
(a3) growing a second oxide layer on the first oxide layer in the select transistor area and the substrate in the memory cell area.
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3. The method of claim 2, wherein the removing step (a2) comprises:
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(a2i) placing a mask on the first oxide layer in the select transistor area;
(a2ii) etching the first oxide layer in the memory cell area; and
(a2iii) removing the mask.
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4. The method of claim 1, wherein the doped amorphous silicon layer is formed using low pressure chemical vapor deposition techniques at about 450-580°
- C. and 300-550 mT with about 1200-3000 sccm of SiH4 and 15-30 sccm of a mixture of 1% by weight of PH3 in He.
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5. The method of claim 1, wherein the forming step (c) comprises:
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(c1) depositing a first dielectric oxide layer on the doped amorphous silicon layer;
(c2) depositing a nitride layer on the first dielectric oxide layer; and
(c3) growing a second dielectric oxide layer on the nitride layer.
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6. The method of claim 1, wherein the forming step (d) comprises:
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(d1) growing a second doped amorphous silicon layer on the insulating layer; and
(d2) growing a tungsten silicide layer on the second doped amorphous silicon layer.
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7. A NAND-type flash memory device, comprising:
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a substrate;
at least one memory cell stack structure on the substrate, comprising;
a tunnel oxide layer, a floating gate on the tunnel oxide layer comprising doped amorphous silicon, the doped amorphous silicon having a dopant level which simultaneously avoids a select transistor word line resistance problem and a charge gain/charge loss problem, wherein the doped amorphous silicon has a dopant level between approximately 5×
1018 and 8×
1019 ions/cm3 of phosphorus, and wherein the select transistor word line resistance is no greater than approximately 1500 ohms per square,a first insulating layer on the floating gate, and a first control gate layer on the first insulating layer; and
at least one select transistor stack structure on the substrate, comprising;
a select gate oxide layer on the substrate, a select gate on the select gate oxide layer comprising the doped amorphous silicon, a second insulating layer on the select gate, and a second control gate layer on the second insulating layer. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14)
a first dielectric oxide layer on the floating gate;
a nitride layer on the first dielectric oxide layer; and
a second dielectric oxide layer on the nitride layer.
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10. The device of claim 7, wherein the second insulating layer comprises:
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a first dielectric oxide layer on the select gate;
a nitride layer on the first dielectric oxide layer; and
a second dielectric oxide layer on the nitride layer.
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11. The device of claim 7, wherein the first control gate layer comprises:
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a polysilicon layer on the first insulating layer; and
a tungsten silicide layer on the polysilicon layer.
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12. The device of claim 7, wherein the second control gate layer comprises:
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a polysilicon layer on the second insulating layer; and
a tungsten silicide layer on the polysilicon layer.
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13. The device of claim 7, wherein the at least one memory cell stack structure further comprises:
a silicon oxynitride layer on the first control gate layer.
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14. The device of claim 7, wherein the at least one select transistor stack structure further comprises:
a silicon oxynitride layer on the second control gate layer.
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15. A method for providing a NAND-type flash memory device, comprising:
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(a) forming a select gate oxide layer in a select transistor area of a substrate and a tunnel oxide layer in a memory cell area of the substrate;
(b) forming a doped amorphous silicon layer on the select gate oxide layer and the tunnel oxide layer, wherein the doped amorphous silicon layer has a dopant level between approximately 5×
1018 and 8×
1019 ions/cm3 of phosphorus;
(c) forming an insulating layer on the doped amorphous silicon layer;
(d) forming a control gate layer on the insulating layer; and
(e) etching at least the doped amorphous silicon layer, the insulating layer, and the control gate layer to form at least one memory cell stack structure and at least one select transistor stack structure, wherein the select transistor word line resistance is no greater than approximately 1500 ohms per square. - View Dependent Claims (16, 17, 18, 19, 20)
(a1) growing a first oxide layer in the select transistor area and the memory cell area;
(a2) removing the first oxide layer in the memory cell area; and
(a3) growing a second oxide layer on the first oxide layer in the select transistor area and the substrate in the memory cell area.
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17. The method of claim 16, wherein the removing step (a2) comprises:
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(a2i) placing a mask on the first oxide layer in the select transistor area;
(a2ii) etching the first oxide layer in the memory cell area; and
(a2iii) removing the mask.
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18. The method of claim 15, wherein the doped amorphous silicon layer is formed using low pressure chemical vapor deposition techniques at about 450-580°
- C. and 300-550 mT with about 1200-3000 sccm of SiH4 and 15-30 sccm of a mixture of 1% by weight of PH3 in He.
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19. The method of claim 15, wherein the forming step (c) comprises:
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(c1) depositing a first dielectric oxide layer on the doped amorphous silicon layer;
(c2) depositing a nitride layer on the first dielectric oxide layer; and
(c3) growing a second dielectric oxide layer on the nitride layer.
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20. The method of claim 15, wherein the forming step (d) comprises:
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(d1) growing a polysilicon layer on the insulating layer; and
(d2) growing a tungsten silicide layer on the polysilicon layer.
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21. A NAND-type flash memory device, comprising:
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a substrate;
at least one memory cell stack structure on the substrate, comprising;
a tunnel oxide layer, a floating gate on the tunnel oxide layer comprising doped amorphous silicon, wherein the doped amorphous silicon has a dopant level between approximately 5×
1018 and 8×
1019 ions/cm3 of phosphorus,a first insulating layer on the floating gate, and a first control gate layer on the first insulating layer; and
at least one select transistor stack structure on the substrate, wherein the select transistor word line resistance is no greater than approximately 1500 ohms per square, comprising;
a select gate oxide layer on the substrate, a select gate on the select gate oxide layer comprising the doped amorphous silicon, a second insulating layer on the select gate, and a second control gate layer on the second insulating layer. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28)
a first dielectric oxide layer on the floating gate;
a nitride layer on the first dielectric oxide layer; and
a second dielectric oxide layer on the nitride layer.
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24. The device of claim 21, wherein the second insulating layer comprises:
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a first dielectric oxide layer on the select gate;
a nitride layer on the first dielectric oxide layer; and
a second dielectric oxide layer on the nitride layer.
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25. The device of claim 21, wherein the first control gate layer comprises:
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a polysilicon layer on the first insulating layer; and
a tungsten silicide layer on the polysilicon layer.
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26. The device of claim 21, wherein the second control gate layer comprises:
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a polysilicon layer on the second insulating layer; and
a tungsten silicide layer on the polysilicon layer.
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27. The device of claim 21, wherein the at least one memory cell stack structure further comprises:
a silicon oxynitride layer on the first control gate layer.
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28. The device of claim 21, wherein the at least one select transistor stack structure further comprises:
a silicon oxynitride layer on the second control gate layer.
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29. A method for providing a NAND-type flash memory device, comprising:
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(a) growing a first oxide layer in a select transistor area of a substrate and a memory cell area of the substrate;
(b) removing the first oxide layer in the memory cell area;
(c) growing a second oxide layer on the first oxide layer in the select transistor area and the substrate in the memory cell area;
(d) forming a doped amorphous silicon layer on the select gate oxide layer and the tunnel oxide layer, wherein the doped amorphous silicon layer has a dopant level between approximately 5×
1018 and 8×
1019 ions/cm3 of phosphorus, wherein the doped amorphous silicon layer is formed using low pressure chemical vapor deposition techniques at about 450-580°
C. and 300-550 mT with about 1200-3000 sccm of SiH4 and 15-30 sccm of a mixture of 1% by weight of PH3 in He;
(e) forming an insulating layer on the doped amorphous silicon layer;
(f) growing a polysilicon layer on the insulating layer;
(g) growing a tungsten silicide layer on the polysilicon layer;
(h) growing a silicon oxynitride layer on the tungsten silicide layer; and
(i) etching at least the doped amorphous silicon layer, the insulating layer, the polysilicon layer, the tungsten silicide layer, and the silicon oxynitride layer to form at least one memory cell stack structure and at least one select transistor stack structure, wherein the select transistor word line resistance is no greater than approximately 1500 ohms per square.
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30. A NAND-type flash memory device, comprising:
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a substrate;
at least one memory cell stack structure on the substrate, comprising;
a tunnel oxide layer, a floating gate on the tunnel oxide layer comprising doped amorphous silicon, wherein the doped amorphous silicon has a dopant level between approximately 5×
1018 and 8×
1019 ions/cm3 of phosphorus, wherein the doped amorphous silicon is formed using low chemical vapor deposition techniques at 450-580°
C. and 300-550 mT with about 1200-3000 sccm of SiH4 and 15-30 sccm of a mixture of 1% by weight of PH3 in He,a first insulating layer on the floating gate, a first polysilicon layer on the first insulating layer, a first tungsten silicide layer on the first polysilicon layer, and a first silicon oxynitride layer on the first tungsten silicide layer; and
at least one select transistor stack structure on the substrate, wherein the select transistor word line resistance is no greater than approximately 1500 ohms per square, comprising;
a select gate oxide layer on the substrate, a select gate on the select gate oxide layer comprising the doped amorphous silicon, a second polysilicon layer on the second insulating layer, a second tungsten silicide layer on the second polysilicon layer, and a second silicon oxynitride layer on the second tungsten silicide layer.
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Specification