ESD protection structure and method

• US 6,218,704 B1
• Filed: 05/07/1997
• Issued: 04/17/2001
• Est. Priority Date: 05/07/1997
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Brown, Jeffrey S., Voldman, Steven H., Leidy, Robert K., Holmes, Steven J.
• Primary Examiner(s): Lee, Eddie C.
• Assistant Examiner(s): Fenty, Jesse A.
• Application Number:
  US08/851,973
• Time in Patent Office: 1,441 Days
• Field of Search: 257/546, 257/355, 257/356, 257/358, 257/398, 257/399, 257/173
• US Class Current: 257/355
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 27/0288 using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to increase the robustness of electrostatic discharge (ESD) protection devices by reducing the temperature gradient caused by ESD pulses and reducing the likelihood of thermal runaway caused by large ESD pulses. The preferred embodiment forms implants under the trench isolation structures in the ESD devices. The implants reduce the current-caused heating that can lead to thermal runaway, and thus improve the robustness of the ESD protection device. In the preferred embodiment, the implants are formed using hybrid resist. The hybrid resist provides a method to form that implants that does not require additional masking steps or other excessive processing. Additionally, the hybrid resist provides implants that are self aligned with the well regions.

Claims

1. A dual-diode electrostatic discharge protection device comprising:

a) a semiconductor substrate;

b) a first diode formed in said semiconductor substrate, the first diode including;

i) a first well formed in said semiconductor substrate, the first well comprising a first diode cathode;

ii) a first diffusion formed in the first well, the first diffusion comprising a first diode anode,

c) a second diode formed in said semiconductor substrate, the second diode including;

i) a second well formed in said semiconductor substrate,

ii) a second diffusion formed in the second well, the second well and the second diffusion comprising a second diode cathode and said semiconductor substrate comprising a second diode anode;

d) at least one implant formed at an edge of the first well;

e) at least one implant formed at an edge of the second well; and

f) an input, the input coupled to the first diffusion and said second diffusion and to a protected device such that the protected device is protected from electrostatic discharge; and

wherein said semiconductor substrate comprises a p-type substrate, wherein said first well comprises a n-type well, wherein said first diffusion comprises a p-type diffusion, wherein the at least one implant formed at an edge of the first well comprises a n-type implant, wherein the second well comprises a n-type well, wherein the second diffusion comprises a n-type diffusion, and wherein the at least one implant formed at an edge of the second well comprises a n-type implant.

2. A dual-diode electrostatic discharge protection device comprising:

a) a semiconductor substrate;

b) a first diode formed in said semiconductor substrate, the first diode including;

i) a first well formed in said semiconductor substrate the first well comprising a first diode cathode;

ii) a first diffusion formed in the first well, the first diffusion comprising a first diode anode;

c) a second diode formed in said semiconductor substrate, the second diode including;

i) a second well formed in said semiconductor substrate,

ii) a second diffusion formed in the second well, the second well and the second diffusion comprising a second diode cathode and said semiconductor substrate comprising a second diode anode;

d) at least one implant formed at an edge of the first well;

e) at least one implant formed at an edge of the second well;

f) an input, the input coupled to the first diffusion and said second diffusion and to a protected device such that the protected device is protected from electrostatic discharge;

g) at least one isolation region formed in said first well; and

h) at least one implant formed under said isolation region in said first well.

3. The dual-diode electrostatic discharge protection device of claim 2 wherein said semiconductor substrate comprises a p-type substrate, wherein said first well comprises a n-type well, and wherein said at least one implant formed under said isolation region in said first well comprises a n-type implant.

4. The dual-diode electrostatic discharge protection device of claim 2 further comprising a n-type diffusion formed in said first well between said isolation region and one of said at least one implant formed at an edge of the first well, and wherein said n-type diffusion is coupled to a high potential.

12. The dual-diode electrostatic discharge protection device of claim 4 further comprising:

i) an isolation region formed between said first n-well and said second n-well;

j) a first p-well formed under said isolation region between said first n-well and said second n-well;

k) at least one p+ implant formed at an edge of said first p-well.

5. A dual-diode electrostatic discharge protection device comprising:

a) a semiconductor substrate;

b) a first diode formed in said semiconductor substrate the first diode including;

i) a first well formed in said semiconductor substrate the first well comprising a first diode cathode;

ii) a first diffusion formed in the first well the first diffusion comprising a first diode anode;

c) a second diode formed in said semiconductor substrate the second diode including;

i) a second well formed in said semiconductor substrate,

ii) a second diffusion formed in the second well the second well and the second diffusion comprising a second diode cathode and said semiconductor substrate comprising a second diode anode;

d) at least one implant formed at an edge of the first well;

e) at least one implant formed at an edge of the second well;

f) an input the input coupled to the first diffusion and said second diffusion and to a protected device such that the protected device is protected from electrostatic discharge;

g) an isolation region formed between said first well and said second well;

h) a third well formed under said isolation region between said first well and said second well;

i) at least one implant formed at an edge of said third well.

6. The dual-diode electrostatic discharge protection device of claim 5 wherein said semiconductor substrate comprises a p-type substrate, wherein said third well well comprises a p-type well, wherein the at least one implant formed at an edge of the third well comprises a p+ implant.

7. The dual-diode electrostatic discharge protection device of claim 5 further comprising:

g) a fourth well formed in said semiconductor substrate;

h) a fourth diffusion formed in said fourth well, said fourth diffusion coupled to a high potential; and

i) at least one implant formed at an edge of said fourth well.

8. The dual-diode electrostatic discharge protection device of claim 7 further comprising

j) an isolation region formed between said fourth well and sand second well;

k) a fifth well formed under said isolation region formed between said fourth well and said second well;

l) at least one implant formed at an edge of said fifth well, the at least one implant formed at an edge of said fifth well combing with said at least one implant formed at an edge of said fourth well and with said at least one implant formed at an edge of said second well to form a buried diode.

9. The dual-diode electrostatic discharge protection device of claim 7 wherein said semiconductor substrate comprises a p-type substrate, wherein said first well comprises a n-type well, wherein said first diffusion comprises a p-type diffusion, wherein the at least one implant formed at an edge of the first well comprises a n-type implant, wherein the second well comprises a n-type well, wherein the second diffusion comprises a n-type diffusion, wherein the at least one implant formed at an edge of the second well comprises a n-type implant, wherein the fourth well comprises a n-type well, wherein the fourth diffusion comprises an n-type diffusion, and wherein the at least one implant formed at an edge of said forth well comprises an n-type implant.

10. The dual-diode electrostatic discharge protection device of claim 7 wherein said semiconductor substrate comprises a p-type substrate, wherein said first well comprises a n-type well, wherein said first diffusion comprises a p-type diffusion, wherein the at least one implant formed at an edge of the first well comprises a n-type implant, wherein the second well comprises a n-type well, wherein the second diffusion comprises a n-type diffusion, wherein the at least one implant formed at an edge of the second well comprises a n-type implant, wherein the fourth well comprises a n-type well;

wherein the fourth diffusion comprises an n-type diffusion, wherein the at least one implant formed at an edge of said forth well comprises an n-type implant, wherein the fifth well comprises a p-type well, and wherein the at least one implant formed at an edge of said fifth well comprises a p-type implant.

11. A dual-diode electrostatic discharge protection device comprising:

a) a p-type semiconductor substrate;

b) a first diode formed in said semiconductor substrate, the first diode including;

i) a first n-well formed in said semiconductor substrate, the first well comprising a first diode cathode;

ii) a first p+ diffusion formed in the first well, the first diffusion comprising a first diode anode;

c) a second diode formed in said semiconductor substrate, the second diode including;

i) a second n-well formed in said semiconductor substrate;

ii) a first n+ diffusion formed in the second well, the second n-well and the first n+ diffusion comprising a second diode cathode and said semiconductor substrate comprising a second diode anode;

d) at least one n+ implant formed at an edge of the first well;

e) at least one n+ implant formed at an edge of the second well,

f) at least one isolation region formed in said first n-well;

g) a n+ diffusion formed in said first n-well between said isolation region and one of said at least one implant formed at an edge of the first n-well, and wherein said n+ diffusion is coupled to a high potential;

h) an input, the input coupled to the fist diffusion and said second diffusion and to a protected device such that the protected device is protected from electrostatic discharge.

13. The dual-diode electrostatic discharge protection device of claim 11 further comprising:

i) a third n-well formed in said semiconductor substrate;

j) a second n+ diffusion formed in said third n-well well, said second n+ diffusion coupled to a high potential; and

k) at least one n+ implant formed at an edge of said third n-well.

14. The dual-diode electrostatic discharge protection device of claim 13 further comprising:

l) an isolation region formed between said third n-well and said second n-well;

o) a second p-well formed under said isolation region formed between said third n-well and said second n-well; and

q) at least one p+ implant formed at an edge of said second p-well, the at least one p+ implant formed at an edge of said second p-well combing with said at least one n+ implant formed at an edge of said third n-well and with said at least one n+ implant formed at an edge of said second n-well to form a buried diode.

15. A dual-diode electrostatic discharge protection device comprising:

a) a p-type semiconductor substrate;

b) a first diode formed in said semiconductor substrate, the first diode including;

i) a first n-well formed in said semiconductor substrate, the first n-well comprising a first diode cathode;

ii) a first p+ diffusion formed in the first well, the first p+ diffusion comprising a first diode anode;

c) a second diode formed in said semiconductor substrate, the second diode including;

i) a second n-well formed in said semiconductor substrate;

ii) a first n+diffusion formed in the second n-well, the second n-well and the second n+ diffusion comprising a second diode cathode and said semiconductor substrate comprising a second diode anode;

d) at least one n+implant formed at an edge of the first n-well;

e) at least one n+implant formed at an edge of the second n-well;

f) at least one isolation region formed in said first n-well;

g) a n+ diffusion formed in said first n-well between said isolation region and one of said at least one implant formed at an edge of the first n-well, and wherein said n+ diffusion is coupled to a high potential;

h) at least one n+ implant formed under said isolation region in said first n-well;

i) an isolation region formed between said first n-well and said second n-well;

j) a first p-well formed under said isolation region between said first n-well and said second n-well;

k) at least one p+ implant formed at an edge of said first p-well;

l) a third n-well formed in said semiconductor substrate;

m) a second n+ diffusion formed in said third n-well, said second n+ diffusion coupled to a high potential;

n) at least one n+ implant formed at an edge of said third n-well;

o) an isolation region formed between said third n-well and said second n-well;

p) a second p-well formed under said isolation region formed between said third n-well and said second n-well;

q) at least one p+ implant formed at an edge of said second p-well, the at least one p+ implant formed at an edge of said second p-well combing with said at least one n+ implant formed at an edge of said third n-well and with said at least one n+ implant formed at an edge of said second n-well to form a buried diode; and

r) an input, the input coupled to the first diffusion and said second diffusion and to a protected device such that the protected device is protected from electrostatic discharge.