Power circuit and clock signal detection circuit

• US 6,218,893 B1
• Filed: 10/07/1998
• Issued: 04/17/2001
• Est. Priority Date: 02/19/1998
• Status: Expired due to Fees

• Current Assignee: Oki Semiconductor Company Limited (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Noguchi, Hidekazu
• Primary Examiner(s): Tran, Toan
• Assistant Examiner(s): NGUYEN, LINH M
• Application Number:
  US09/167,670
• Time in Patent Office: 923 Days
• Field of Search: 327/72, 327/73, 327/77, 327/78, 327/79, 327/80, 327/81, 327/87, 327/88, 327/89, 327/543, 327/540, 327/544, 365/189.09, 365/226, 365/227
• US Class Current: 327/540
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

A power circuit includes an internal voltage regulation portion, a response time regulation portion, p-channel type field-effect transistors (FET) which serve as a voltage transformation portion, and a clock signal detection circuit. An external voltage input to the power circuit is transformed into an internal voltage which is set by a reference voltage, and the variance of the internal voltage may be compensated by the internal voltage regulation portion. Also, the response speed of the internal voltage regulation portion to the variance of the internal voltage may be regulated by the response time regulation portion. The clock signal detection portion detects a clock signal and switches an n-channel type FET in the response time regulation portion to an active state, thereby enhancing the response speed of the internal voltage regulation portion. Accordingly, the power circuit ensures stabilized output of power and effective power saving as well.

Claims

1. A power circuit which is provided in a synchronous dynamic random access memory device that operates synchronously with a clock signal input thereto, the power circuit comprising:

a voltage transformation portion that transforms an external voltage into an internal voltage, the internal voltage having a level lower than a level of the external voltage;

an internal voltage regulation portion that monitors the internal voltage and outputs to said voltage transformation portion a first control signal that controls the voltage transformation in response to the internal voltage;

a response time regulation portion that regulates output response time of the first control signal based on a second control signal; and

a clock signal detection circuit that detects the clock signal and outputs the second control signal responsive thereto,

said clock signal detection circuit including a charge/discharge circuit that charges an output node synchronized with a rising edge and a falling edge of the clock signal.

2. The power circuit as claimed in claim 1, wherein a discharge time of the output node of said charge/discharge circuit is set longer than a period of the clock signal.

3. The power circuit as claimed in claim 1, wherein said clock signal detection circuit comprises:

a first one-shot pulse generating circuit that generates a one-shot pulse synchronized with the rising edge of the clock signal; and

a second one-shot pulse generating circuit that generates a one-shot pulse synchronized with the falling edge of the clock signal.

4. A power circuit which is provided in a synchronous dynamic random access memory device that operates synchronously with a clock signal input thereto, the power circuit comprising:

a voltage transformation portion that transforms an external voltage into an internal voltage, the internal voltage having a level lower than a level of the external voltage;

an internal voltage regulation portion that monitors the internal voltage and outputs to said voltage transformation portion a first control signal that controls the voltage transformation in response to the internal voltage;

a response time regulation portion that regulates output response time of the first control signal based on a second control signal; and

a clock signal detection circuit that detects the clock signal and outputs the second control signal responsive thereto,

said clock signal detection circuit including

a first charge/discharge circuit having a first output node, that charges the first output node synchronized with a falling edge of the clock signal and that starts discharging the first output node synchronized with a rising edge of the clock signal,

a second charge/discharge circuit having a second output node, that charges the second output node synchronized with the rising edge of the clock~ signal and that starts discharging the second output node synchronized with the falling edge of the clock signal, and

an exclusive NOR gate having a first input terminal connected to the first output node, a second input terminal connected to the second output node and an output terminal that provides the second control signal.

5. The power circuits as claimed in claim 4, wherein discharge times of said first and second charge/discharge circuits are set longer than a period of the clock signal.

6. A power circuit which is provided in a synchronous dynamic random access memory device that operates synchronously with a clock signal input thereto, the power circuit comprising:

a voltage transformation portion that transforms an external voltage into an internal voltage, the internal voltage having a level lower than a level of the external voltage;

an internal voltage regulation portion that monitors the internal voltage and outputs to said voltage transformation portion a first control signal that controls the voltage transformation in response to the internal voltage;

a response time regulation portion that regulates output response time of the first control signal based on a second control signal; and

a clock signal detection circuit that detects the clock signal and outputs the second control signal responsive thereto,

said response time regulation portion being operational in accordance with a plurality of operational modes of the synchronous dynamic random access memory device, including at least an active standby mode.

7. A power circuit which is provided in a synchronous dynamic random access memory device that operates synchronously with a clock signal input thereto, the power circuit comprising:

a voltage transformation portion that transforms an external voltage into an internal voltage, the internal voltage having a level lower than a level of the external voltage;

an internal voltage regulation portion that monitors the internal voltage and outputs to said voltage transformation portion a first control signal that controls the voltage transformation in response to the internal voltage;

a response time regulation portion that regulates output response time of the first control signal based on a second control signal; and

a clock signal detection circuit that detects the clock signal and outputs the second control signal responsive thereto,

the clock signal being input to the synchronous dynamic random access memory device, or being made valid within the synchronous dynamic random access memory device, when a data writing operation or a data reading operation is executed, and

the clock signal not being input to the synchronous dynamic random access memory device, or being made invalid within the synchronous dynamic random access memory device, when the data writing operation or the data reading operation is not executed.

8. A power circuit which is provided in a synchronous dynamic random access memory device that operates synchronously with a clock signal input thereto, the power circuit comprising:

a voltage transformation portion that transforms an external voltage into an internal voltage, the internal voltage having a level lower than a level of the external voltage;

an internal voltage regulation portion that monitors the internal voltage and outputs to said voltage transformation portion a first control signal that controls the voltage transformation in response to the internal voltage;

a response time regulation portion that regulates output response time of the first control signal based on a second control signal; and

a clock signal detection circuit that detects the clock signal and outputs the second control signal responsive thereto,

the clock signal not being input to the synchronous dynamic random access memory device, or being made invalid within the synchronous dynamic random access memory device, during a first time period when the synchronous dynamic random access memory device receives an active command and does not receive a data read command or a data write command, and

the clock signal being input to the synchronous dynamic random access memory device, or being made valid within the synchronous dynamic random access memory device, during a second time period just after the first time period when the synchronous dynamic random access memory device receives the data read command or the data write command.

9. A method of providing an operating voltage to a synchronous dynamic random access memory device that operates synchronously with a clock signal input thereto, comprising:

transforming an external voltage into an internal voltage for supply to the memory device as the operating voltage, the internal voltage having a level lower than a level of the external voltage;

monitoring the internal voltage and generating a first control signal responsive to the internal voltage that controls said transforming;

regulating an output response time of the first control signal based on a second control signal; and

detecting the clock signal and generating the second control signal responsive thereto,

said detecting comprising charging and discharging the second control signal as synchronized with a rising edge and a falling edge of the clock signal.

10. The method of providing an operating voltage of claim 9, wherein a discharge time of said charging and discharging is set longer than a period of the clock signal.

11. The method of providing an operating voltage of claim 9, wherein said charging and discharging comprises generating a one-shot pulse synchronized with the rising edge of the clock signal and generating a one-shot pulse synchronized with the falling edge of the clock signal.

12. A method of providing an operating voltage to a synchronous dynamic random access memory device that operates synchronously with a clock signal input thereto, comprising:

transforming an external voltage into an internal voltage for supply to the memory device as the operating voltage, the internal voltage having a level lower than a level of the external voltage;

monitoring the internal voltage and generating a first control signal responsive to the internal voltage that controls said transforming;

regulating an output response time of the first control signal based on a second control signal; and

detecting the clock signal and generating the second control signal responsive thereto,

said detecting including

charging a first signal as synchronized with a falling edge of the clock signal, discharging of the first signal beginning as synchronized with a rising edge of the clock signal,

charging a second signal as synchronized with the rising edge of the clock signal, discharging of the second signal beginning as synchronized with the falling edge of the clock signal, and

performing a logical exclusive-NOR operation on the first and second signals to provide the second control signal.

13. The method of providing an operating voltage of claim 12, wherein discharge times of the first and second signals are set longer than a period of the clock signal.