Method and apparatus for driving an active matrix display panel

• US 6,219,113 B1
• Filed: 12/17/1997
• Issued: 04/17/2001
• Est. Priority Date: 12/17/1996
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Takahara, Hiroshi
• Primary Examiner(s): Sikes, William I.
• Assistant Examiner(s): CHOWDHURY, TARIFUR RASHID
• Application Number:
  US08/993,250
• Time in Patent Office: 1,217 Days
• Field of Search: 349/42, 349/43, 349/45, 345/92, 345/98, 345/100
• US Class Current: 349/42
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/1334 based on polymer dispersed liquid crystals, e.g. microencapsulated liquid crystals
• CPC Class Codes: G02F 1/133521 Interference filters
• CPC Class Codes: G02F 1/133526 Lenses, e.g. microlenses or Fresnel lenses
• CPC Class Codes: G02F 1/133553 Reflecting elements associated to illuminating devices G02F1/133605
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/1347 Arrangement of liquid crystal layers or cells in which the final condition of one light beam is achieved by the addition of the effects of two or more layers or cells
• CPC Class Codes: G02F 1/136259 Repairing; Defects
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2201/34 reflector
• CPC Class Codes: G02F 2202/104 poly-Si
• CPC Class Codes: G09G 2300/0434 Flat panel display in which a field is applied parallel to the display plane
• CPC Class Codes: G09G 2310/0283 Arrangement of drivers for different directions of scanning
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3655 Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
• CPC Class Codes: H04N 9/3105 for displaying all colours simultaneously, e.g. by using two or more electronic spatial light modulators simultaneous projection in colour photography G03B33/10; beam splitting or combining systems per se G02B27/10
• CPC Class Codes: H04N 9/3144 Cooling systems cooling of liquid crystal cells in general G02F1/133382; cooling of projectors not peculiar to the presence of an electronic spatial light modulator G03B21/16
• CPC Class Codes: H04N 9/3167 for polarizing the light beam polarizing optical systems per se G02B27/28

Abstract

An array substrate 12 is formed with pixel electrodes 14 in the form of a matrix. The pixel electrode 14 is connected to a thin film transistor 155. The thin film transistor 155 is formed with a light shielding film 152 consisting of resin for preventing an entry of light into the thin film transistor 155. A polymer dispersion liquid crystal layer 21 is interposed between a counter electrode 25 and the pixel electrode 14. A substrate 11 is formed with a color filter 151 having red (R), green (G), and blue (B). The color filter 151 is formed from dielectric multilayer film or organic material. The counter electrode 25 is formed above the color filter 155, and the counter electrode 25 and the liquid crystal layer 21 are bonded together by an adhesive layer 371.

Claims

1. An active matrix display panel fabricated with a low-temperature polysilicon technique, the active matrix display panel having an effective display area and a diagonal length of D (inch), comprising:

at least one source signal line coupled to said display panel;

a source driver circuit for applying a video signal to the source signal line;

at least one P-channel transistor having (a) a drain coupled to the source signal line, (b) a source for receiving the video signal and (c) a transfer gate coupled to the source driver circuit for switchably connecting the video signal to the source signal line; and

said transfer gate having a width, W (μ

m), and a length, L (μ

m),

wherein W/L is related to D by $10<br><br>D\le <br><br>\frac{W}{L}\le <br><br>50<br><br>D.$

2. The active matrix display panel according to claim 1, wherein a plurality of inverter circuits are connected between a shift register of said source driver circuit and said transfer gate, and

the following relationship holds:

3. The active matrix display panel according to claim 1, wherein a plurality of inverter circuits are connected between a shift register of said source driver circuit and said transfer gate, and

the following relationship holds:

4. An active matrix display panel fabricated with a low-temperature polysilicon technique, the active matrix display panel having an effective display area and a diagonal length of D (inch), comprising:

at least one source signal line coupled to said display panel;

a source driver circuit for applying a video signal to the source signal line;

at least one P-channel transistor having (a) a drain coupled to the source signal line, (b) a source for receiving the video signal and (c) a transfer gate coupled to the source driver circuit for switchably connecting the video signal to the source signal line; and

said transfer gate having a width, W (μ

m), and a length, L (μ

m),

wherein W/L is related to D by $\frac{200<br><br>\text{\hspace{1em}<br><br>}<br><br>D}{{\mathrm{\mu <br><br>}}_p}\le <br><br>\frac{W}{L}\le <br><br>\frac{1200<br><br>\text{\hspace{1em}<br><br>}<br><br>D}{{\mathrm{\mu <br><br>}}_p}$

and μ

_p is a mobility of the P-channel transistor.

5. The active matrix display panel according to claim 4, wherein a plurality of inverter circuits are connected between a shift register of said source driver circuit and said transfer gate, and

the following relationship holds:

6. The active matrix display panel according to claim 4, wherein a plurality of inverter circuits are connected between a shift register of said source driver circuit and said transfer gate, and

the following relationship holds:

7. An active matrix display panel fabricated with a low-temperature polysilicon technique, comprising

at least one source signal line coupled to said display panel;

a source driver circuit for applying a video signal to the source signal line;

at least one transistor including (a) a drain coupled to the source signal line, (b) a source for receiving the video signal and (c) a transfer gate coupled to the source driver circuit for switchably connecting the video signal to the source signal line; and

a plurality of inverter circuits coupled between the transfer gate and the source driver circuit;

one of said inverter circuits including a P-channel transistor and an N-channel transistor, said P-channel and N-channel transistors each including a respective gate connected together;

the gate of the P-channel transistor having a width W_p (μ

m) and a length L_p (μ

m), and the gate of the N-channel transistor having a width W_s (μ

m) and a length L_s (μ

m);

wherein the following relationship is satisfied;

$0.4\le <br><br>\frac{\frac{W_s}{L_s}}{\frac{W_p}{L_p}}\le <br><br>0.8.$

8. The active matrix display panel according to claim 7, wherein said N-channel transistor has a low-doped drain structure and a mobility μ

n of 50≦

μ

n≦

150.

9. An active matrix display panel fabricated with a low-temperature polysilicon technique, comprising

at least one source signal line coupled to said display panel;

a source driver circuit for applying a video signal to the source signal line;

at least one transistor including (a) a drain coupled to the source signal line, (b) a source for receiving the video signal and (c) a transfer gate coupled to the source driver circuit for switchably connecting the video signal to the source signal line; and

a plurality of inverter circuits serially connected between the transfer gate and the source driver circuit;

a first inverter of said inverter circuits including a first P-channel transistor, the first P-channel transistor having a gate of width W<sub>n−

1</sub> (μ

m) and a length of L_n (μ

m);

a second inverter of said inverter circuits connected to the first inverter, wherein the second inverter is previous in position to the first inverter, and includes a second P-channel transistor, the second P-channel transistor having a gate of width W<sub>n−

1</sub> (μ

m) and a length of L<sub>n−

1</sub> (μ

m);

wherein the following relationship is satisfied;

$0.25\le <br><br>\frac{\frac{W_{n-1}}{L_{n-1}}}{\frac{W_n}{L_n}}\le <br><br>0.75.$

10. The active matrix display panel according to claim 9, wherein said N-channel transistor has a low-doped drain structure and a mobility μ

n of 50≦

μ

n≦

150.

11. A display comprising:

light generation means;

a light guiding plate which transmits light generated by said light generation means;

an active matrix display panel fabricated with a low-temperature polysilicon technique, the active matrix display panel having an effective display area and a diagonal length of D (inch), including;

at least one source signal line coupled to said display panel;

a source driver circuit for applying a video signal to the source signal line;

at least one P-channel transistor having (a) a drain coupled to the source signal line, (b) a source for receiving the video signal and (c) a transfer gate coupled to the source driver circuit for switchably connecting the video signal to the source signal line; and

said transfer gate having a width, W (μ

m), and a length, L (μ

m),

wherein W/L is related to D by $10<br><br>\text{\hspace{1em}<br><br>}<br><br>D\le <br><br>\frac{W}{L}\le <br><br>50<br><br>D;<br><br>$

 

first polarization means disposed between said light guiding plate and said active matrix display panel; and

second polarization means disposed on a light exit side of said display panel.

12. A display comprising:

light generation means;

a light guiding plate which transmits light generated by said light generation means;

an active matrix display panel fabricated with a low-temperature polysilicon technique, the active matrix display panel having an effective display area and a diagonal length of D (inch), including;

at least one source signal line coupled to said display panel;

a source driver circuit for applying a video signal to the source signal line;

at least one P-channel transistor having (a) a drain coupled to the source signal line, (b) a source for receiving the video signal and (c) a transfer gate coupled to the source driver circuit for switchably connecting the video signal to the source signal line; and

said transfer gate having a width, W (μ

m), and a length, L (μ

m),

wherein W/L is related to D by $\frac{200<br><br>\text{\hspace{1em}<br><br>}<br><br>D}{{\mathrm{\mu <br><br>}}_p}\le <br><br>\frac{W}{L}\le <br><br>\frac{1200<br><br>\text{\hspace{1em}<br><br>}<br><br>D}{{\mathrm{\mu <br><br>}}_p}$

 

and μ

_p is a mobility of the P-channel transistor;

first polarization means disposed between said light guiding plate and said active matrix display panel; and

second polarization means disposed on a light exit side of said display panel.

13. A display comprising:

light generation means;

a light guiding plate which transmits light generated by said light generation means;

an active matrix display panel fabricated with a low-temperature polysilicon technique, including;

at least one source signal line coupled to said display panel;

a source driver circuit for applying a video signal to the source signal line;

at least one transistor including (a) a drain coupled to the source signal line, (b) a source for receiving the video signal and (c) a transfer gate coupled to the source driver circuit for switchably connecting the video signal to the source signal line; and

a plurality of inverter circuits coupled between the transfer gate and the source driver circuit;

one of said inverter circuits including a P-channel transistor and an N-channel transistor, said P-channel and N-channel transistors each including a respective gate connected together;

the gate of the P-channel transistor having a width W_p (μ

m) and a length L_p (μ

m), and the gate of the N-channel transistor having a width W_s (μ

m) and a length L_s (μ

m);

wherein the following relationship is satisfied;

$0.4\le <br><br>\frac{\frac{W_s}{L_s}}{\frac{W_p}{L_p}}\le <br><br>0.8;<br><br>$

 

first polarization means disposed between said light guiding plate and said active matrix display panel; and

second polarization means disposed on a light exit side of said display panel.

14. A display comprising:

light generation means;

a light guiding plate which transmits light generated by said light generation means;

an active matrix display panel fabricated with a low-temperature polysilicon technique, including;

at least one source signal line coupled to said display panel;

a source driver circuit for applying a video signal to the source signal line;

at least one transistor including (a) a drain coupled to the source signal line, (b) a source for receiving the video signal and (c) a transfer gate coupled to the source driver circuit for switchably connecting the video signal to the source signal line; and

a plurality of inverter circuits serially connected between the transfer gate and the source driver circuit;

a first inverter of said inverter circuits including a first P-channel transistor, the first P-channel transistor having a gate of width W_n (μ

m) and a length of L_n (μ

m);

a second inverter of said inverter circuits connected to the first inverter, wherein the second inverter is previous in position to the first inverter, and includes a second P-channel transistor, the second P-channel transistor having a gate of width W<sub>n−

1</sub> (μ

m) and a length of L<sub>n−

1</sub> (μ

m);

wherein the following relationship is satisfied;

$0.25\le <br><br>\frac{\frac{W_{n-1}}{L_{n-1}}}{\frac{W_n}{L_n}}\le <br><br>0.75;<br><br>$

 

first polarization means disposed between said light guiding plate and said active matrix display panel; and

second polarization means disposed on a light exit side of said display panel.