Multilevel cell programming

• US 6,219,276 B1
• Filed: 02/25/2000
• Issued: 04/17/2001
• Est. Priority Date: 02/25/2000
• Status: Expired due to Term

• Current Assignee: Valley Device Management
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Parker, Allan
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): NGUYEN, HIEN N
• Application Number:
  US09/513,643
• Time in Patent Office: 417 Days
• Field of Search: 365/185.03, 365/185.29, 365/185.19, 365/185.17, 365/185.02, 365/185.33
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 2211/5644 Multilevel memory comprising counting devices

Abstract

Method of storing and retrieving multiple bits of information in a multi-level cell of non-volatile memory including programming a plurality of multi-level memory cells within a programming time target. The multi-level memory cells having at least first, second, third and fourth programming levels. The fourth programming level being the erase state, the first programming level being the programming level furthest from the fourth programming level. The second and third programming levels being within the first and fourth programming levels, includes erasing the plurality of multi-level memory cells. Then, programming a first group of multi-level memory cells with the first programming level with a first programming pulse count having a first pulse width and a first programming voltage. Then, programming a second group of multi-level memory cells with the second programming level with a second programming pulse count having a second pulse width and a second programming voltage. Then programming a third group of multi-level memory cells with the third programming level with a third programming pulse count having a third pulse width and a third programming voltage.

Claims

1. A method of programming a plurality of multi-level memory cells within a programming time target, the multi-level memory cells having at least first, second, third and fourth programming levels, the fourth programming level being the erase state, the first programming level being the programming level furthest from the fourth programming level, the second and third programming levels being within the first and fourth programming levels, comprising:

erasing the plurality of multi-level memory cells;

programming a first group of multi-level memory cells with the first programming level with a first programming pulse count, a first pulse width, and a first programming voltage;

programming a second group of multi-level memory cells with the second programming level with a second programming pulse count, a second pulse, width and a second programming voltage; and

programming a third group of multi-level memory cells with the third programming level with a third programming pulse count, a third pulse width, and a third programming voltage.

2. The method of claim 1, wherein the plurality of multi-level memory cells comprises a page of multi-level NAND memory cells.

3. The method of claim 1, wherein the cells are multi-level flash memory cells.

4. The method of claim 1, wherein the first, second, third, and fourth programming levels are approximately 2.0V, 1.0V, 0.0V, and−

2.5V respectively.

5. The method of claim 1, wherein the second pulse width is 5 to 10 microseconds.

6. The method of claim 1, wherein the first pulse width is 3 to 6 microseconds.

7. The method of claim 1, wherein the second programming voltage is 17 to 19 volts.

8. The method of claim 1, wherein the third programming voltage is 18 to 20 volts.

9. The method of claim 1, wherein the first programming pulse count is the minimum pulse count required to program the cell.

10. The method of claim 1, wherein the second programming pulse count is selected to maintain at least 85% of the maximum programming margin.

11. The method of claim 10, wherein the third programming pulse count is substantially the same as the second programming pulse count.

12. The method of claim 10, wherein the second pulse width is selected such that the combination of the programming times for the first, second, and third programming levels is within the programming time target.

13. The method of claim 12, wherein the third pulse width is substantially the same as the second pulse width.

14. The method of claim 13, wherein the third programming voltage programs the cell to the third programming level with the third programming pulse count of the third pulse width, the third programming voltage being an offset of the second programming voltage.

15. A memory device, comprising:

(a) a plurality of memory cells capable of being programmed with a first, second, third, and fourth voltage levels, each voltage level corresponding to a plurality of bits of information, the plurality of memory cells comprising a first, second, third, and fourth group of cells;

(b) a pulse count determination means for determining first, second, and third pulse counts for programming the first, second, and third group of cells, respectively;

(c) a program voltage determination means for determining first, second, and third program voltages for programming the first, second, and third group of cells, respectively; and

(d) a cell programming means for programming each of the plurality of cells in the plurality of memory cells with the first, second, third, and four voltage levels, the cell programming means programming the plurality of memory cells with the fourth voltage level, then programming the first group of cells to the first voltage level using the first program voltage and the first pulse count, then programming the second group of cells to the second voltage level using the second program voltage and the second pulse count, then programming the third group of cells to the third voltage level using the third program voltage and the third pulse count.

16. A memory device, comprising:

(a) a plurality of memory cells capable of being programmed with a first, second, third, and fourth voltage levels, each voltage level corresponding to a plurality of bits of information, the plurality of memory cells including a first, second, third, and fourth group of cells;

(b) a pulse count determinator capable of determining a first, second, and third pulse counts for programming the first, second, and third group of cells, respectively;

(c) a program voltage determinator being capable of determining a first, second, and third program voltages for programming the first, second, and third group of cells, respectively; and

(d) a cell programmer capable of programming each of the plurality of cells in the plurality of memory cells with the first, second, third, and four voltage levels, the cell programmer programming the plurality of memory cells with the fourth voltage level, then programming the first group of cells to the first voltage level using the first program voltage and the first pulse count, then programming the second group of cells to the second voltage level using the second program voltage and the second pulse count, then programming the third group of cells to the third voltage level using the third program voltage and the third pulse count.

17. The memory device of claim 16, wherein the fourth voltage level is the erase voltage level.

18. The memory device of claim 16, wherein the cell programmer includes a cell erase circuit and a cell programming circuit, the cell erase circuit being capable of erasing one or more of the plurality of cells, the cell programming circuit being capable of programming one or more of the plurality of cells to the first, second, and third voltage levels.

19. The memory device of claim 16, wherein the second pulse width is selected such that the combination of the programming times for the first, second, and third programming levels is within the programming time target.

20. The memory device of claim 16, wherein the second programming pulse count is selected to maintain at least 85% of the maximum programming margin.