Method and system for measuring signal propagation delays using ring oscillators

• US 6,219,305 B1
• Filed: 07/14/1998
• Issued: 04/17/2001
• Est. Priority Date: 09/17/1996
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Chung, Daniel, Young, Steven P., Conn, Robert O., Wells, Robert W., Kingsley, Christopher H., Patrie, Robert D.
• Primary Examiner(s): MISKA, VIT W
• Application Number:
  US09/114,369
• Time in Patent Office: 1,008 Days
• Field of Search: 368/110-113, 368/118-120, 327/265, 324/73.R, 324/73.AT, 324/76.77, 324/76.8, 324/617, 324/763, 324/765, 371/22.1, 371/22.5, 371/25.1, 371/27, 371/28, 714/733
• US Class Current: 368/113
• CPC Class Codes: G01R 27/04 in circuits having distributed constants , e.g. having very long conductors or involving high frequencies
• CPC Class Codes: G01R 31/2853 Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66
• CPC Class Codes: G01R 31/2882 Testing timing characteristics
• CPC Class Codes: G01R 31/3016 Delay or race condition test, e.g. race hazard test
• CPC Class Codes: G01R 31/31725 Timing aspects, e.g. clock distribution, skew, propagation delay for tester hardware G01R31/31937
• CPC Class Codes: G01R 31/318516 Test of programmable logic devices [PLDs]

Abstract

A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with an inverting feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. These signal transitions are counted over a predetermined time period to establish the average period of the oscillator. Finally, the average period of the oscillator is related to the average signal propagation delay through the test circuit. One embodiment of the invention includes a phase discriminator that samples the output of the oscillator and accumulates data representing the duty cycle of that signal. The duty cycle can then be combined with the average period of the test signal to determine, separately, the delays associated with falling and rising edges propagating through the test circuit.

Claims

1. A system for determining a maximum signal propagation delay through a test circuit having a test-circuit input node and a test-circuit output node, the system comprising:

a. an inverting element having an inverting-element input node connected to the test-circuit output node and an inverting-element output node connected to the test-circuit input node, wherein the inverting element and the test circuit combine to form a ring oscillator providing a test signal comprised of alternating rising and falling signal transitions;

b. a counter having a counter input node and at least one counter output node, the counter input node being connected to the test circuit, the counter adapted to count the number of signal transitions of the test signal; and

c. a phase discriminator having at least one phase-discriminator input node connected to one of the test-circuit input and output nodes, the phase discriminator adapted to output a variable for calculating the duty cycle of the test signal.

2. The system of claim 1, wherein the phase discriminator includes a sample clock sequentially producing alternating rising and falling signal transitions on a sample-clock node.

3. The system of claim 2, wherein the sample clock is adapted to produce a plurality of sample-clock frequencies.

4. The system of claim 3, wherein the plurality of sample-clock frequencies are prime with respect to one another.

5. The system of claim 2, wherein the sample clock is a phase noise-generator.

6. The system of claim 2, wherein the sample clock is controlled by a shift register.

7. The system of claim 6, wherein the sample clock is controlled by a linear-feedback shift register.

8. The system of claim 1, wherein the test circuit is configured in an FPGA configured to include the counter and the phase discriminator.

9. The system of claim 2, the phase discriminator having a second phase-discriminator input node connected to the sample-clock node, and a test-circuit output node, wherein the phase discriminator samples the test signal between rising and falling signal transitions of the test signal at a sample rate determined by the sample clock.

10. The system of claim 9, wherein the test signal is sampled when the test signal is a logic zero.

11. The system of claim 9, wherein the test signal is sampled when the test signal is a logic one.

12. The system of claim 2, wherein the sample-clock node connects to a clock input of the phase discriminator.

13. A system for determining a maximum signal propagation delay through a test circuit having a test-circuit input node and a test-circuit output node. the system comprising:

a. an inverting element having an inverting-element input node connected to the test-circuit output node and an inverting-element output node connected to the test-circuit input node, wherein the inverting element and the test circuit combine to form a ring oscillator providing a test signal comprised of alternating rising and falling signal transitions on the test-circuit input node;

b. a counter having a counter input node and a counter output node, the counter input node being connected to the test circuit, the counter adapted to count the number of signal transitions of the test signal; and

c. a phase discriminator having;

i. a sample clock sequentially producing alternating rising and falling signal transitions on a sample-clock node;

ii. a second phase-discriminator input node connected to the sample-clock node;

iii. a phase-discriminator output node;

iv. first and second phase comparators, each phase comparator having a first input node connected to the test circuit and adapted to receive the test signal, a second input connected to the sample-clock node, and a phase-comparator output node, wherein the first phase comparator samples the test signal between rising and falling signal transitions of the test signal at a sample rate determined by the sample clock when the test signal is a logic one, and the second phase comparator samples the test signal between rising and falling signal transitions of the test signal at a sample rate determined by the sample clock when the test signal is a logic zero;

d. wherein the phase discriminator produces a variable for calculating the duty cycle of the test signal.

15. The system of claim 13, further comprising a first counter having an input node connected to the output node of the first phase comparator and a second counter having an input node connected to the output node of the second phase comparator.

14. A system for determining a maximum signal propagation delay through a test circuit having a test-circuit input node and a test-circuit output node, the system comprising:

a. an inverting element having an inverting-element input node connected to the test-circuit output node and an inverting-element output node connected to the test-circuit input node, wherein the inverting element and the test circuit combine to form a ring oscillator providing a test signal comprised of alternating rising and falling signal transitions on the test-circuit input node;

b. a counter having a counter input node and a counter output node, the counter input node being connected to the test circuit, the counter adapted to count the number of signal transitions of the test signal;

c. a phase discriminator having;

i. a sample clock sequentially producing alternating rising and falling signal transitions on a sample-clock node;

ii. a second phase-discriminator input node connected to the sample-clock node; and

iii. a phase-discriminator output node; and

d. a counter having an input node connected to the phase-discriminator output node;

e. wherein the phase discriminator samples the test signal between rising and falling signal transitions of the test signal at a sample rate determined by the sample clock; and

f. wherein the phase discriminator produces a variable for calculating the duty cycle of the test signal.

16. A method of measuring a signal propagation delay time required for a rising signal transition to traverse a test circuit having a test-circuit input node and a test-circuit output node, the method comprising:

a. providing a train of alternating rising and falling signal transitions on the test-circuit input node, thereby producing a test signal comprising the alternating rising and falling signal transitions on the test-circuit output node;

b. measuring the period of the test signal; and

c. measuring the duty cycle of the test signal.

17. The method of claim 16, wherein measuring the period of the test signal comprises counting a number of test-signal periods over a predetermined time.

18. The method of claim 16, further comprising independently deriving, from the duty cycle and the period, a first signal propagation delay for rising edges traversing the test circuit and a second signal propagation delay for falling edges traversing the test circuit.

19. The method of claim 16, wherein the test signal comprises a series of alternating high and low logic levels, and wherein measuring the duty cycle of the test signal comprises sampling the test signal during the high and low logic levels at random sampling intervals.

20. The method of claim 19, further comprising generating the random sampling intervals using a phase noise-generator.

21. A method of measuring a signal propagation delay time required for a rising signal transition to traverse a test circuit having a test-circuit input node and a test-circuit output node, the method comprising:

a. providing a train of alternating rising and falling signal transitions on the test-circuit input node, thereby producing a test signal comprising the alternating rising and falling signal transitions on the test-circuit output node;

b. measuring the period of the test signal; and

c. measuring the duty cycle of the test signal;

d. wherein the test signal comprises a series of alternating high and low logic levels, and wherein measuring the duty cycle of the test signal comprises;

sampling the test signal during the high logic levels at a sample rate to determine a first variable; and

sampling the test signal during the low logic levels at the sample rate to determine a second variable.

22. The method of claim 21, further comprising:

a. sampling the test signal during the high logic levels at a second sample rate different from the first sample rate; and

b. sampling the test signal during the low logic levels at the second sample rate.

23. The method of claim 22, further comprising:

a. sampling the test signal during the high logic levels at a third sample rate different from the first and second sample rates;

b. sampling the test signal during the low logic levels at the third sample rate;

c. calculating the duty cycle for each of the first, second and third sample rates to obtain corresponding first, second, and third measured duty cycles; and

d. comparing the first, second, and third measured duty cycles.

24. The method of claim 23, further comprising discarding any one of the first, second, and third duty cycles that is not consistent with the remaining two.

25. A circuit for measuring a signal-propagation delay time required for a rising signal transition to traverse a test circuit having a test-circuit input node and a test-circuit output node, the circuit comprising:

a. means for providing a train of alternating rising and falling signal transitions on the test-circuit input node, thereby producing a test signal comprised of a delayed series of alternating rising and falling signal transitions on the test circuit output node;

b. means for measuring the period of the test signal; and

c. means for measuring the duty cycle of the test signal.

26. The circuit of claim 25, further comprising means for independently deriving, from the duty cycle and the period, a first signal propagation delay for rising edges traversing the test circuit and a second signal propagation delay for falling edges traversing the test circuit.

27. A system for determining a maximum signal propagation delay through a test circuit having a test-circuit input node and a test-circuit output node, the system comprising:

a. a ring oscillator including the test circuit and adapted to connect the test-circuit input node to the test-circuit output node, the ring oscillator providing a test signal comprised of alternating rising and falling signal transitions on the test-circuit input node and on the test-circuit output node;

b. means for measuring a duty cycle of the test signal;

c. means for measuring a period of the test signal; and

d. means for independently deriving, from the duty cycle and the period, a first signal propagation delay for rising edges traversing the test circuit and a second signal propagation delay for falling edges traversing the test circuit.

28. The system of claim 27, wherein the means for measuring the duty cycle of the test signal includes at least one phase comparator.

29. The system of claim 27, wherein the means for measuring the period of the test signal includes at least one counter.

30. A system for determining a maximum signal propagation delay through a test circuit having a test-circuit input node and a test-circuit output node, the system comprising:

a. a signal path connected between the test-circuit input node and the test-circuit output node, wherein the signal path and the test circuit combine to form a ring oscillator providing a test signal comprised of alternating rising and falling signal transitions on a plurality of test-circuit nodes;

b. a circuit having an input terminal connected to at least one of the test-circuit nodes and adapted to determine the period of the test signal; and

c. a phase discriminator having at least one phase-discriminator input node connected to at least one of the test-circuit nodes and adapted to output at least one variable for calculating the duty cycle of the test signal.

31. The system of claim 30, further comprising test circuitry adapted to calculate, from the period and duty cycle of the test signal, a first signal propagation delay for rising edges traversing the test circuit and a second signal propagation delay for falling edges traversing the test circuit.

32. The system of claim 31, wherein the signal path is an inverting signal path.