Pulse position modulation based transceiver architecture with fast acquisition slot-locked-loop

• US 6,219,380 B1
• Filed: 01/06/1998
• Issued: 04/17/2001
• Est. Priority Date: 04/28/1997
• Status: Expired due to Term

• Current Assignee: Transpacific IP Group Limited
• Original Assignee: Industrial Technology Research Institute
• Inventors: Dan, Ten-Long, Huang, Kuang-Hu, Wang, Wei-Chen, Wang, Chorng-Kuang
• Primary Examiner(s): VO, DON NGUYEN
• Application Number:
  US09/003,485
• Time in Patent Office: 1,197 Days
• Field of Search: 375/239, 375/345, 375/359, 375/360, 375/361, 375/376, 375/219, 329/313, 329/314, 332/112
• US Class Current: 375/239
• CPC Class Codes: H03K 7/04 Position modulation, i.e. PPM
• CPC Class Codes: H04B 14/026 using pulse time characteristics modulation, e.g. width, position, interval
• CPC Class Codes: H04L 25/4902 Pulse width modulation; Pulse position modulation

Abstract

A transceiver has a pulse position modulation (PPM) encoder, automatic gain control (AGC) circuit and timing recovery circuit. The PPM encoder illustratively has a frequency divider, slot selector, and mixer. The frequency divider divides the frequency of a clock signal to which the data of the non-return to zero (NRZ) signal are aligned to produce a half frequency clock signal. The slot selector selects pulses of the clock signal and the half frequency clock signal depending on logic values of the NRZ signal and a control signal to produce first and second slot selected signals. The mixer mixes the first and second slot selected signals to produce a PPM signal of the NRZ signal. The AGC circuit illustratively has a variable gain amplifier, a hysteresis comparator, an event detector, a timer, and a counter. The variable gain amplifier amplifies the PPM signal using a dynamically adjusted gain that depends on an inputted digital control value. The counter increments the inputted digital control value according to a clock signal outputted from the timer to increase the gain. The hysteresis comparator detects a signal level of the amplified PPM signal. The event detector causes the counter to decrease the inputted digital control value if the signal level is outside of a predetermined signal level range. The timing recovery circuit has a frequency track, a slot locked loop and a phase locked loop. The frequency track generates a coarse clock fx having a frequency that depends on a frequency of the PPM signal. The slot locked loop generates a resampling clock signal having a frequency that depends on the course clock fx and having slots locked to slots of the PPM signal. The phase locked loop locks a phase of the coarse clock fx to a phase of the PPM signal.

Claims

1. A method for pulse position modulating a non-return to zero signal (NRZ) comprising the steps of:

(a) dividing the frequency of a clock signal to which the data of the NRZ signal are aligned to produce a half frequency clock signal,

(b) selecting pulses of said clock signal and said half frequency clock signal depending on logic values of said NRZ signal and a control signal to produce first and second slot selected signals, and

(c) mixing said first and second slot selected signals to produce a PPM signal of said NRZ signal.

2. The method of claim 1 further comprising the steps of:

(d) eliminating a haze in said PPM signal.

3. The method of claim 1 wherein said NRZ signal has a frequency of X MHz, wherein said PPM signal is a 2ⁱ-ary PPM signal, where i is an integer,

wherein said step (a) comprises producing i−

1 clock signals A₀, A_l, . . . , A_i-2, wherein each of said clock signals A_j has a frequency of 2^i-1/[2^j·

(i−

1)]·

X MHz, for 0≦

j≦

i−

2, and

wherein said step (b) comprises modulating, each of said clock signals A_j with a corresponding j^th bit of an i−

1 bit symbol formed from i−

1 bits of said NRZ signal, and combining said modulated clock signals to produce one of said first and second slot select signals.

4. A pulse position modulation encoder for encoding a non-return to zero (NRZ) signal comprising:

(a) a frequency divider receiving a clock signal to which the data of the NRZ signal are aligned and dividing said clock signal to produce a half frequency clock signal,

(b) a slot selector receiving said clock signal, said half frequency clock signal said NRZ signal, and a control signal, and selecting pulses of said clock signal and said half frequency clock signal depending on logic values of said NRZ signal and a control signal to produce first and second slot selected signals, and

(c) a mixer receiving said first and second slot selected signals and mixing said first and second slot selected signals to produce a PPM signal of said NRZ signal.

5. The pulse position modulation encoder of claim 4 further comprising:

(d) a haze eliminator, receiving said PPM signal and eliminating a haze in said PPM signal.

6. The pulse position modulation encoder of claim 4 wherein said NRZ signal has a frequency of X MHZ, wherein said PPM signal is a 2ⁱ-ary PPM signal, where i is an integer,

wherein said frequency divider comprises a counter producing i−

1 clock signals A₀, A₁, . . . , A_i-2, wherein each of said clock signals A_j has a frequency of 2^i-1/[2^j·

(i−

1)]·

X MHz, for 0≦

j≦

i−

2, and

wherein said slot selector comprises a plurality of first logic gates, including one first logic gate corresponding to each of said clock signals A_j, each of said first logic gates modulating said corresponding clock signal A_j with a corresponding j^th bit of an i−

1 bit symbol formed from i−

1 bits of said NRZ signal, said slot selector also comprising a second logic gate for combining said modulated clock signals to produce one of said first and second slot select signals.

7. A method for locking synchronization to a pulse position modulated (PPM) signal comprising the steps of:

(a) generating a coarse clock fx having a frequency that depends on a frequency of said PPM signal,

(b) generating a resampling clock signal having a frequency that depends on said coarse clock fx and slots locked to slots of said PPM signal, and

(c) locking a phase of said coarse clock fx to a phase of said PPM signal.

8. The method of claim 7 wherein said step (a) further comprises the steps of:

(a1) counting the number N of clock pulses of a reference clock between rising edges of said PPM signal on which a sequence of logic ‘

1’

data bits is modulated, and

(a2) generating said coarse clock fx having a frequency that depends on a frequency of said PPM signal on which said sequence of logic ‘

1’

data bits is modulated.

9. The method of claim 7 wherein said step (b) further comprises the steps of:

(b1) selecting specific slots of said coarse clock fx as determined by dynamically varying slot selection signals,

(b2) comparing pulses of said resampling clock signal to said PPM signal to determine a phase error between said resampling PPM signal and said PPM signal,

(b3) if said phase error exceeds 90°

, varying said slot selection signals.

10. The method of claim 9 wherein said slot selection signals are one or more bits of a count, said step (b3) further comprising the step of incrementing said count.

11. The method of claim 7 wherein said step (c) further comprises the steps of:

(c1) determining a polarity of a phase error between said coarse clock fx and said PPM signal, and

(c2) inserting or deleting a pulse into said coarse clock fx depending on a polarity of said phase error.

12. A timing recovery circuit for locking synchronization to a pulse position modulated (PPM) signal comprising:

(a) a frequency track receiving said PPM signal and generating a coarse clock fx having a frequency that depends on a frequency of said PPM signal,

(b) a slot locked loop receiving said PPM signal and said coarse clock and generating a resampling clock signal fs having a frequency that depends on said coarse clock fx and having slots locked to slots of said PPM signal, and

(c) a phase locked loop receiving said PPM signal and said coarse clock fx and locking a phase of said coarse clock fx to a phase of said PPM signal.

13. The timing recovery circuit of claim 12 wherein said frequency track further comprises:

(a1) a counter receiving said PPM signal and counting the number N of clock pulses of a reference clock between rising edges of said PPM signal on which a sequence of logic ‘

1’

data bits is modulated, and

(a2) a counter receiving a value that depends on said number N and generating said coarse clock fx having a frequency that depends on a frequency of said PPM signal on which said sequence of logic ‘

1’

data bits is modulated.

14. The timing recovery circuit of claim 12 wherein said slot locked loop comprises:

(b1) a PPM encoder receiving said coarse clock, selecting specific slots of said coarse clock fx as determined by dynamically varying slot selection signals and generating said resampling clock fs with pulses in selected slots,

(b2) a slot detector receiving said resampling clock and said PPM signal, comparing pulses of said resampling clock signal to said PPM signal to determine a phase error between said resampling PPM signal and said PPM signal and outputting a control signal if said phase error exceeds 90°

, and

(b3) a circuit receiving said control signal outputted from said slot detector and varying said slot selection signals.

15. The timing recovery circuit of claim 14 wherein said circuit is a counter, wherein said slot selection signals are one or more bits of a count, said counter incrementing said count in response to said control signal.

16. The timing recovery circuit of claim 12 wherein said phase locked loop comprises:

(c1) a phase detector receiving said coarse clock fs and said PPM signal, determining a polarity of a phase error between said coarse clock fx and said PPM signal, and outputting an increment or decrement control signal depending on said polarity, and

(c2) a counter receiving said increment and decrement control signal and inserting or deleting a pulse into said coarse clock fx in response to said increment or decrement signal, respectively.

17. A transceiver comprising:

a pulse position modulation encoder comprising;

a frequency divider receiving a clock signal to which the data of a to-be-transmitted NRZ signal are aligned and dividing said clock signal to produce a half frequency clock signal,

a slot selector receiving said clock signal, said half frequency clock signal said NRZ signal, and a control signal, and selecting pulses of said clock signal and said half frequency clock signal depending on logic values of said NRZ signal and a control signal to produce first and second slot selected signals, and

a mixer receiving said first and second slot selected signals and mixing said first and second slot selected signals to produce a transmitted PPM signal of said NRZ signal,

an automatic gain control circuit for regulating the signal level of a received PPM signal comprising;

a variable gain amplifier receiving said received PPM signal and an inputted digital control value and amplifying said received PPM signal using a dynamically adjusted gain that depends on said inputted digital control value,

a counter for incrementing said inputted digital control value according to a clock signal to increase said gain, and

a circuit for receiving said amplified PPM signal, detecting a signal level of said amplified signal, and if said detected signal level is outside of a predetermined signal level range, outputting a signal to said counter for decreasing said inputted digital control value to decrease said gain, and

a timing recovery circuit for locking synchronization to said amplified PPM signal comprising;

a frequency track receiving said amplified PPM signal and generating a coarse clock fx having a frequency that depends on a frequency of said amplified PPM signal,

a slot locked loop receiving said amplified PPM signal and said coarse clock and generating a resampling clock signal fs having a frequency that depends on said coarse clock fx and having slots locked to slots of said amplified PPM signal, and

a phase locked loop receiving said amplified PPM signal and said coarse clock fx and locking a phase of said coarse clock fx to a phase of said amplified PPM signal.