Radio communication apparatus

• US 6,219,534 B1
• Filed: 02/09/1999
• Issued: 04/17/2001
• Est. Priority Date: 02/09/1998
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Torii, Kenichi
• Primary Examiner(s): Maung, Nay
• Assistant Examiner(s): Vuong, Quochien B.
• Application Number:
  US09/247,082
• Time in Patent Office: 798 Days
• Field of Search: 455/63, 455/296, 455/295, 455/302, 455/303, 455/67.1, 455/67.3, 455/226.1, 455/226.4, 455/501, 375/346, 375/348, 375/349
• US Class Current: 455/303
• CPC Class Codes: H03D 3/009 Compensating quadrature phase or amplitude imbalances
• CPC Class Codes: H03D 7/166 using two or more quadrature frequency translation stages
• CPC Class Codes: H04B 1/123 using adaptive balancing or compensation means adaptive filter circuits and algorithms H03H
• CPC Class Codes: H04L 27/2332 using a non-coherent carrier

Abstract

A radio communication apparatus comprises an analog I/Q signal generator, a digital demodulator, and an interference wave suppression control block. The interference wave suppression block detects a gain difference between an in-phase component and a double quadrature component, based on an input and output signals of a low pass filter in the digital demodulator and the output of the double quadrature mixer, and controls a reference voltage of an A/D converter in the digital demodulator. Therefore, it is possible to reduce the gain difference of the in-phase component and the quadrature component, and to effectively eliminate an interference wave mixed in a base band signal. Furthermore, a radio communication apparatus according to the present invention comprises an antenna input block, a reception block, a transmission block, and an in/out block. Because a frequency when sending data is equal to the frequency when receiving data, it is possible to quickly change transmission and reception. Accordingly, it is possible to effectively use time-slots and transfer data at high speed.

Claims

1. A radio communication apparatus, comprising:

a first in-phase/quadrature component separating circuit for separating a selecting frequency component included in a signal received by an antenna into an in-phase component signal and a quadrature component signal;

a first A/D converter for outputting a digital signal obtained through an A/D converter of the in-phase component signal separated by said first in-phase/quadrature component separating circuit;

a second A/D converter for outputting a digital signal obtained through an A/D conversion of the quadrature component signal separated by said first in-phase/quadrature component separating circuit;

a detecting circuit for performing a detecting process based on the digital signals outputted from said first and second A/D converters;

a second in-phase/quadrature component separating circuit for separating the digital signal outputted from said first A/D converter into the in-phase component signal and the quadrature component signal;

a third in-phase/quadrature component separating circuit for separating the digital signal outputted from said second A/D converter into the in-phase component signal and the quadrature component signal; and

an interference wave suppression control circuit for controlling at least one of reference voltages of said first and second A/D converters based on each signal separated by said second and third in-phase/quadrature component separating circuits, so that the gain difference of each digital signal outputted from said first and second A/D converters is equal to or less than a prescribed value.

2. The radio communication apparatus according to claim 1, comprising:

a first adder for adding the in-phase component signal separated by said second in-phase/quadrature component separating circuit and the quadrature component signal separated by the third in-phase/quadrature component; and

a second adder for adding the second quadrature component signal separated by said second in-phase/quadrature component separating circuit and the in-phase component signal separated by the third in-phase/quadrature component separating circuit, wherein

said interference wave suppression control circuit controls at least one of said reference voltages of said first and second A/D converters based on the output of either said first adder or said second adder.

3. The radio communication apparatus according to claim 2, further comprising:

a first low pass filter for reducing a high frequency component included in an output of said first adder; and

a second low pass filter for reducing the high frequency component included in an output of said second adder, wherein

said detecting circuit performs a detecting process based on the outputs of said first and second low pass filters; and

said interference wave suppression control circuit controls the reference voltage of said first A/D converter based on the in-phase component signal separated by said second in-phase/quadrature component separating circuit, the output of said first adder, and the output of said first low pass filter.

4. The radio communication apparatus according to claim 3, wherein

said interference wave suppression control circuit includes:

a first delay circuit for delaying the output signal of said first adder for almost the same period as would be necessary to pass through said first low pass filter;

a second delay circuit for delaying the in-phase component signal separated by said second in-phase/quadrature component separating circuit for a period necessary to pass through said first adder and said first low pass filter;

an amplitude converting circuit for converting the output amplitude of said first low pass filter into almost a half value,

a first subtracter for calculating and outputting a difference between the output of said first delay circuit and the output of said first low pass filter;

a second subtracter for calculating and outputting a difference between the output of said amplitude converting circuit and the output of said second delay circuit;

a third adder for adding the outputs of said first and subtracters;

a first peak detector for detecting a peak level of the output of said first subtracter;

a second peak detector for detecting the peak level of the output of said second subtracter;

a third peak detector for detecting the peak level of the output of said third subtracter;

a level comparator for comparing an amplitude level of the outputs of said second and third peak detectors;

a sign changer for outputting the peak level detected by said first peak detector with plus or minus sign attached thereto;

a D/A converter for converting the output of said sign changer into an analog signal; and

a third low pass filter for reducing a high frequency component included in the output of said D/A converter, wherein

a reference voltage of said first A/D converter is controlled based on the output of said third low pass filter.

5. The radio communication apparatus according to claim 4, wherein

said interference wave suppression control circuit raises the reference voltage of said first A/D converter when the output level of said third peak detector is higher than that of said second peak detector, and lowers the reference voltage of said first A/D converter when the output level of said third peak detector is lower than that of said second peak detector.

6. The radio communication apparatus according to claim 1, wherein

at least one of said first and second A/D converters includes a fourth adder for generating said reference voltage by adding a prescribed voltage of which the voltage level is constant and the output voltage of said interference wave suppression control circuit, a voltage dividing circuit for outputting a plurality of voltages which are generated by dividing said reference voltage at a prescribed ratio, a plurality of comparators for comparing analog input voltages with each voltage outputted from said voltage dividing circuit, and an encoder for converting said analog input signal into the digital signal based on the comparative result of said comparator.

7. The radio communication apparatus according to claim 1, wherein

at least one of said first and second A/D converters includes a reference voltage generating circuit for generating said reference voltage based on a difference between a voltage obtained by adding a prescribed voltage of which the voltage level is constant and the output voltage of said interference wave suppression control circuit, and a voltage obtained by adding an inverse voltage of said prescribed voltage and an inverse output voltage of said interference wave suppression control circuit, a voltage dividing circuit for outputting a plurality of voltages which are generated by dividing said reference voltage at a prescribed ratio, a plurality of comparators for comparing an analog input voltage with each voltage outputted from said voltage dividing circuit, and an encoder for converting said analog input signal into the digital signal, based on the comparative result of said comparators.

10. The radio communication apparatus according to claim 1, wherein said A/D converter includes a reference voltage generating circuit for generating said reference voltage by using a difference between a voltage obtained by adding a prescribed voltage of which the voltage level is constant and the output voltage of said interference wave suppression control circuit, and a voltage obtained by adding an inverse voltage of said prescribed voltage and an inverse output voltage of said interference wave suppression control circuit, a voltage dividing circuit for outputting a plurality of voltages which are generated by dividing said reference voltage at prescribed ratio, a plurality of comparators for comparing an analog voltage with each voltage outputted from said voltage dividing circuit, and an encoder for converting said analog input signal into said digital signal based on the comparative result of each of said comparators.

8. A radio communication apparatus, comprising:

a first in-phase/quadrature component separating circuit for separating a selecting frequency component included in a signal received by an antenna into an in-phase component signal and a quadrature component signal;

a signal selecting circuit for selecting either the in-phase component signal or the quadrature component signal separated by said first in-phase/quadrature component separating circuit;

an A/D converter for outputting a digital signal obtained through an A/D conversion of the signal selected by said signal selecting circuit;

a delay circuit for delaying the digital signal outputted from said A/D converter;

a second in-phase/quadrature component separating circuit for separating the output of said delay circuit into an in-phase component signal and the quadrature component signal;

a third in-phase/quadrature component separating circuit for separating the digital signal outputted from said A/D converter into an in-phase component signal and a quadrature component signal; and

an interference wave suppression control circuit for controlling the reference voltage of said A/D converter based on each signal separated by said second and third in-phase/quadrature component separating circuits, so that a gain difference of each digital signal outputted from said A/D converter or said delay circuit is equal to or less than a prescribed value.

9. The radio communication apparatus according to claim 8, wherein

said A/D converter includes a fourth adder for generating said reference voltage by adding a prescribed voltage of which the voltage level is constant and the output voltage of said interference wave suppression control circuit, a voltage dividing circuit for outputting a plurality of voltages which are generated by dividing said reference voltage at a prescribed ratio, a plurality of comparators for comparing an analog voltage with each voltage outputted from said voltage dividing circuit, and an encoder for converting said analog input signal into a digital signal based on the comparative result of each of said comparators.