Architecture of a chip having multiple processors and multiple memories

• US 6,219,627 B1
• Filed: 07/12/1994
• Issued: 04/17/2001
• Est. Priority Date: 12/26/1991
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Guttag, Karl, Gove, Robert, Bonneau, Walt C.
• Primary Examiner(s): Maung, Zarni
• Application Number:
  US08/274,132
• Time in Patent Office: 2,471 Days
• Field of Search: 364/488-491, 347/51, 395/800, 703/1, 298/27
• US Class Current: 703/1
• CPC Class Codes: G06F 13/1663 Access to shared memory
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0203 Particular design considerations for integrated circuits
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10T 29/49121 Beam lead frame or beam lead device

Abstract

A method of manufacturing integrated circuits uses an architecture having multiple processors and multiple memories, such that there is at least first and second groups of processors and memories. The first group has at least a first processor and at least a first memory. The second group has at least a second processor and at least a second memory. Regardless of where the architecture is sliced, the integrated circuits have a majority of the same address and data pin-outs.

Claims

1. A method of manufacturing integrated circuits using semiconductor chips, comprising the steps of:

a. making an architecture having multiple instances of a modular unit including a processor, a memory and a crossbar link disposed therebetween, said crossbar links of said modular units connected together providing direct communication between any processor and any memory of a predetermined number of said multiple modular units, and having input/output pads for connecting said architecture to external circuits;

b. grouping said modular units into at least first and second groups, including in each group at least one of said modular units;

c. selecting a first desired number of modular units for a first integrated circuit;

d. slicing said architecture between any two groups, to give said selected number of modular units;

e. repositioning said input/output pads;

f. terminating said connection between crossbar links at said slicing between said two groups;

g. constructing an integrated circuit having said selected first desired number of modular units; and

h. repeating steps d, e, f and g for a second desired number of processors,

wherein said first desired number of processors is different from said second desired number of processors, and wherein said integrated circuits have a majority of the same address and data pin-outs, regardless of said number of modular units chosen.

2. The method of claim 1 including the further step of arranging placement of said groups so that said groups are symmetrical.

3. The method of claim 2 wherein said symmetry is arranged so that if a first part of said architecture is flipped over onto a second part of said architecture, said processors are facing each other, and said memories are facing each other.

4. The method of claim 2 wherein said symmetry is arranged so that if a first part of said architecture is flipped over onto a second part of said architecture, said groups are mirror images of each other.

5. The method of claim 1 wherein a first subset of said modular units are disposed on a first semiconductor chip and a second subset of said modular units are disposed on a second semiconductor chip, and the chips are bonded together by connection of said crossbar links of a predetermined modular unit disposed on said first chip and a predetermined modular unit disposed on said second chip.

6. The method of claim 1 wherein said step of making said architecture further includes making a nonmodular unit to be included in every integrated circuit manufactured.

7. The method of claim 6 wherein said nonmodular unit includes a master processor, a master memory and a master crossbar link disposed therebetween and connected to said crossbar link of an adjacent modular unit, said master crossbar link and said crossbar links of said modular units together providing direct communication between said master processor and said master memory and any memory of a predetermined number of said multiple modular units, and further providing direct communication between said processor of any modular unit and said master memory.

8. The method of claim 7 wherein said nonmodular unit includes a transfer/memory controller connected to said master crossbar link and to at least one external device, said transfer processor providing communication between said master processor, said processors of each modular unit and said at least one external device.

9. The method of claim 6 wherein said nonmodular unit includes a frame controller.

10. The method of claim 6 wherein said nonmodular unit includes a master clock distributed to all portions of said integrated circuit.

11. A method of manufacturing integrated circuits, comprising the steps of:

a. providing a design of a nonmodular unit including at least an input/output circuit having a predetermined plurality of input and output connections;

b. selecting a maximum number of modular units to be included in said integrated circuits;

c. providing a design of a modular unit including a processor, a memory and a crossbar link disposed therebetween, said crossbar links of said modular units connected together providing direct communication between any processor and any memory of up to said selected maximum number of said modular units;

d. selecting a first desired number of modular units no more than said maximum number of modular units for a first integrated circuit;

e. forming a first final design including said nonmodular unit and said first desired number of modular units, said first final design connecting said crossbar links of said modular units in a serial chain;

f. constructing a first integrated circuit according to said first final design;

g. selecting a second desired number of modular units no more than said maximum number of modular units for a second integrated circuit, wherein said second desired number of modular units is different from said first desired number of modular units;

h. forming a second final design including said nonmodular unit and said second desired number of modular units, said second final design connecting said crossbar links of said modular units in a serial chain, said second final design sharing a majority of the same input and output connections including said input and output connections of said nonmodular unit; and

i. constructing a second integrated circuit according to said second final design.

12. The method of claim 11 wherein said design of said nonmodular unit includes a master processor, a master memory and a master crossbar link disposed therebetween and connected to said crossbar link of an adjacent modular unit, said master crossbar link and said crossbar links of said modular units together providing direct communication between said master processor and said master memory and any memory of a predetermined number of said multiple modular units, and further providing direct communication between said processor of any modular unit and said master memory.

13. The method of claim 12 wherein said design of said nonmodular unit includes a transfer/memory controller connected to said master crossbar link and to at least one external device, said transfer processor providing communication between said master processor, said processors of each modular unit and said at least one external device.

14. The method of claim 11 wherein said design of said nonmodular unit includes a frame controller.

15. The method of claim 11 wherein said design of said nonmodular unit includes a master clock distributed to all portions of said integrated circuit.