Universal serial bus (USB) RAM architecture for use with microcomputers via an interface optimized for integrated services device network (ISDN)
First Claim
1. A RAM-based interrupt-driven interface device for establishing a communication link between a high performance serial bus host and a microcontroller device for providing a control function, the interface being operative to receive digital information in the form of command, data and control packets from the host and to process the packets and communicate the processed digital information to the microcontroller device, and in response thereto, the microcontroller device being operative to communicate digital information to the interface device for processing and transfer to the host, comprising:
- means for receiving through said serial bus, a command generated by the host;
means for storing the host-generated command and for generating an interface device interrupt signal upon storage of said host-generated command for use by the microcontroller device in responding to the host-generated command;
a microcontroller bus for transferring digital information and said interface device interrupt signal between the interface device and the microcontroller device;
means for receiving a microcontroller command from the microcontroller device in response to said interface device interrupt signal; and
means for storing said microcontroller command and operative to generate a microcontroller device interrupt signal, upon storage of said microcontroller command, for use by the interface device in developing an address for selection of the interface device by the host during subsequent communications therebetween;
wherein during communication between the host and the interface device, the interface device-developed address is used by the interface device to identify host-provided packet information, and upon processing of the host-provided information, to allow the interface device to respond to the host, thereby allowing a generic microcontroller device to be flexibly interfaced with a high performance serial bus host for communication therebetween.
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Accused Products
Abstract
A RAM-based interrupt-driven interface device is disclosed for establishing a communication link between a universal serial bus (USB) host and a microcontroller device for providing a control function, the interface device being operative to receive digital information in the form of command, data and control packets from the host and to process the packets and communicate the processed digital information to the microcontroller device, and in response thereto, the microcontroller device being operative to communicate digital information to the interface device for processing and transfer thereof to the host. The interface device includes means for receiving a command generated by the host through a USB bus, means for storing the host-generated command and for generating an interface device interrupt signal upon storage of said host-generated command for use by the microcontroller device in responding to the host-generated command, a microcontroller bus for transferring microcontroller information and the interface device interrupt signal between the interface device and the microcontroller device. The interface device further includes means for receiving a microcontroller command from the microcontroller device in response to said interface device interrupt signal and means for storing the microcontroller command and it is operative to generate a microcontroller device interrupt signal upon storage of the microcontroller command for use by the interface device in developing an address for identification of the interface device to the host during subsequent communications therebetween, wherein during communication between the host and the interface device, the interface device-developed address is used by the interface device to identify host-provided information in the form of packets, and upon processing of the host-provided information, to provide the microcontroller device with the necessary information to allow it to respond to the host thereby allowing a generic microcontroller device to be flexibly interfaced with a USB, host for communication therebetween.
182 Citations
35 Claims
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1. A RAM-based interrupt-driven interface device for establishing a communication link between a high performance serial bus host and a microcontroller device for providing a control function, the interface being operative to receive digital information in the form of command, data and control packets from the host and to process the packets and communicate the processed digital information to the microcontroller device, and in response thereto, the microcontroller device being operative to communicate digital information to the interface device for processing and transfer to the host, comprising:
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means for receiving through said serial bus, a command generated by the host;
means for storing the host-generated command and for generating an interface device interrupt signal upon storage of said host-generated command for use by the microcontroller device in responding to the host-generated command;
a microcontroller bus for transferring digital information and said interface device interrupt signal between the interface device and the microcontroller device;
means for receiving a microcontroller command from the microcontroller device in response to said interface device interrupt signal; and
means for storing said microcontroller command and operative to generate a microcontroller device interrupt signal, upon storage of said microcontroller command, for use by the interface device in developing an address for selection of the interface device by the host during subsequent communications therebetween;
wherein during communication between the host and the interface device, the interface device-developed address is used by the interface device to identify host-provided packet information, and upon processing of the host-provided information, to allow the interface device to respond to the host, thereby allowing a generic microcontroller device to be flexibly interfaced with a high performance serial bus host for communication therebetween. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
means to signal the host that a “
re-try”
is required; and
means to “
re-initialize”
the appropriate endpoint register to prepare it for the re-try attempt.
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13. A RAM-based interrupt-driven interface device as recited in claim 6 wherein each of the endpoint registers includes (protocol specific) “
- Sequence”
support for maintaining packet sequence information, including sequence adjustments appropriate to error detection and re-try.
- Sequence”
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14. A RAM-based interrupt-driven interface device as recited in claim 1 including means (“
- auto-NAK”
) for automatically informing the host when the interface device is busy and unable to respond to the host.
- auto-NAK”
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15. A RAM-based interrupt driven interface device as recited in claim 1 wherein the host and the microcontroller device communicate through the USB bus in conformance with a standard USB protocol.
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16. A RAM-based interrupt driven interface device as recited in claim 1 including means for responding to specific “
- device”
commands from the microcontroller that perform device specific operations within the interface device.
- device”
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17. A RAM-based interrupt driven interface device as recited in claim 1 including means for responding to specific “
- pass-through”
commands by passing the command and associated information across the serial bus to the host.
- pass-through”
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18. A RAM-based interrupt driven interface device as recited in claim 1 further including an ISDN interface for causing the interface device to communicate with the host therethrough.
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19. A RAM-based interrupt driven interface device as recited in claim 1 including means for detecting any “
- Start of Frame”
information appearing on the serial bus, and generating an external “
clock”
signal available to external circuitry.
- Start of Frame”
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20. A RAM-based interrupt-driven serial interface device for establishing a communication link between a high performance serial bus host and a microcontroller device providing a control function, the interface device being operative to receive digital information in the form of information packets from the host and to process the packets and store the processed digital information in RAM memory buffers, then to generate an interrupt signal to the microcontroller device, and in response thereto, the microcontroller device being operative to access digital information stored in particular locations in the RAM memory buffers, and in response to said information, to write other information into other locations in the RAM memory buffers, then generate an interrupt signal to the interface device, which then interprets said other information, comprising:
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timing and control means for controlling storage of data buffer descriptor information describing the particular RAM memory buffers;
dual port RAM means including data storage buffers, a descriptor storage buffer and means for permitting independent access to said descriptor storage buffer by both the microcontroller device and the serial interface device;
means by which the microcontroller device can signal said timing and control means that said descriptor storage buffer has been initialized;
hardware based storage means for storing descriptor information describing particular locations in said data storage buffers, such information to be used dynamically while transferring data to and from the high-performance serial bus and the data storage buffers described by the data buffer descriptor information, said timing and control means and said dual port RAM means being further operative to access said descriptor storage buffer and to copy the descriptor contents into said hardware based storage means, and being further operative to manage said data transfer between the data storage buffers and the serial bus;
means for generating interrupt signals for signaling the microcontroller device upon completion of the data transfer between the serial bus and the data storage buffer described by said descriptor contents;
means for receiving address information and read and write strobes from the microcontroller device for accessing the described data storage buffer so that data can be exchanged between the dual port RAM means and the microcontroller device;
means for inhibiting storage of serial transfers from the host after an interrupt signal is sent to the microcontroller device thereby allowing the microcontroller to access uncorrupted data from the described data storage buffer;
means for receiving an interrupt signal from said microcontroller device signaling that access to the data storage buffer has been completed and that a data storage buffer described by the descriptor contents is available for use;
means for disabling said inhibit means so that additional data transfer between the high performance serial bus and the data storage buffer can occur;
means for detecting errors occurring during data transfers and for reinitializing said descriptor storage buffer for use in a “
re-try”
attempt; and
means for indicating that an error has occurred during data transfers and for signaling the host via the high performance serial bus that a “
re-try”
is required.- View Dependent Claims (21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35)
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Specification